M9703B Datasheet, PDF (3/20 Pages) Keysight Technologies – AXIe High-Speed Digitizer/ Wideband Digital Receiver

03 | Keysight | M9703B AXIe High-Speed Digitizer/Wideband Digital Receiver - Data Sheet
Hardware platform
Product overview
The M9703B is a flexible modular wideband digital receiver/
digitizer offering scalable features depending on application
requirements. The standard configuration implements 8 channels
of 12-bit resolution with DC to 650 MHz input frequency range
(–3 dB analog bandwidth), and acquiring data at 1 GS/s. If higher
speed is required, the -SR2 option enables the eight channels
to sample at 1.6 GS/s. An interleave option (-INT) also allows
two channels to be combined and reach 3.2 GS/s in 4-channel
acquisition mode. For higher frequency signals, the -F10 option
provides an extended input frequency range of DC up to 2 GHz
in non interleaved mode, or DC up to 1.4 GHz when interleaving
channels¹.
The architecture is modular and extensible, with an offer of
several AXIe chassis of 2-, 5- and 14-slot, to provide a fully
operational system.
Installing five M9703B digitizers in the M9505A 5-slot AXIe
chassis allows up to 40 channels to be synchronized.
Installing eight M9703B digitizers in the M9514A 14-slot AXIe
chassis allows up to 64 channels to be synchronized.
Data processing
The M9703B implements four Xilinx Virtex-6 FPGAs dedicated to
data processing. The four data processing units (DPU) implement
a standard digitizer functionality firmware by default, allowing
digitization of the signal, storage of the resulting data in the
on-board memory and transfer through the PCIe backplane bus.
The four DPUs may optionally feature a real-time digital
downconversion (DDC) IP algorithm if ordered with the -DDC or
the -LDC options. The DDC allows tuning and zooming on the
signals to be analyzed, improving the dynamic range, reducing
the noise floor, extending the capture time, and accelerating the
measurement speed.
If streaming and recording capability are requested, the -CB1 or
-CB2 options should be considered.
The -LDC option is especially suited for MIMO and multi-channel
BBIQ applications. It provides up to 80 MHz of real-time
frequency span (analysis bandwidth) per channel when combined
with the -SR2 option (up to 50 MHz with -SR1).
Block diagram
DPU A
DC
IN 1 _Front-
End
ADC
IN 2
DC
Front-
ADC
End
DPU B
DC
IN 3 _Front-
End
ADC
IN 4
DC
Front-
ADC
End
DPU C
DC
IN 5 _Front-
End
ADC
IN 6
DC
Front-
ADC
End
DPU D
DC
IN 7 _Front-
End
ADC
IN 8
DC
Front-
ADC
End
TRG 1
TRG 2
TRG 3
TRG OUT
REF IN
CLK IN
Time base
FPGA
Real-Time
Processing
Memory and
Acquisition Control
DDR3
Memory
DDR3
Memory
FPGA
Real-Time
Processing
Memory and
Acquisition Control
DDR3
Memory
DDR3
Memory
FPGA
Real-Time
Processing
Memory and
Acquisition Control
DDR3
Memory
DDR3
Memory
FPGA
Real-Time
Processing
Memory and
Acquisition Control
DDR3
Memory
DDR3
Memory
PCIe
Switch
CTRL FPGA
100 MHz reference clock
Figure 1. Simplified block diagram of the M9703B AXIe Digitizer.
The M9703B also provides open access to its on-board
processing FPGAs for custom algorithm implementation using the
-FDK option. This can be reached through the SystemVue control
software W1462BP FPGA Architect, providing an automatic push
button programming approach.
Alternatively the U5340A FPGA Development Kit can be used
to implement custom algorithms to distribute across multiple
M9703B.
For demanding applications, the -DDC option extends the
real-time frequency span/analysis bandwidth to up to 300 MHz.
Both -LDC and -DDC allow to vary the center frequency from DC
to 1.6 GHz² independently per channel.
1.  The fact that there is less frequency range when interleaving channels is due to internal characteristics of the analog-to-digital converter chipset adding
filters when combining channels.
2.  If -F10 option is ordered, otherwise limits to 650 MHz.