M8020A Datasheet, PDF (27/36 Pages) Keysight Technologies – J-BERT M8020A High-Performance BERT

27 | Keysight | J-BERT M8020A High-Performance BERT - Data Sheet
Pattern, sequencer and interactive link training
Table 20. Specifications for pattern, sequencer and link training.
PRBS ¹
PRBS
Mark density
Zero substitution
Export/Import
Pattern library
User definable memory
Interactive link training
Coding
Scrambler
Vector/sequence
granularity
Pattern capture
Pattern sequencer
2ⁿ-1, n= 7, 10, 11, 15, 23, 23p ³, 31
2ⁿ, n = 7, 10, 11, 13, 15, 23
Mark density: PRBS 1/8 to 7/8
Yes
Patterns from N4900 series can be imported
Yes
2 Gbit/channel ⁴
Link training state machine (LTSSM) for PCIe 3⁴ to achieve loopback state via
recovery with or without link training. Is suitable for testing downstream and
upstream ports according to PCI Express Architecture PHY Test Specification.
Supports the following tests:
2.3 Add-in Card Transmitter Initial Tx EQ Test for 8 GT/s
2.4 Add-in Card Transmitter Link Equalization Response Test for 8 GT/s
2.7 System Board Transmitter Link equalization Response Test for 8 GT/s
2.10 Add-in Card Receiver Link Equalization Test for 8 GT/s
2.11 System Board Receiver Link Equalization Test for 8 GT/s
–– The LTSSM reports to a log file: states, de-emphasis requests by DUT
–– Supported channels: 1, 2 ²
8B/10B, 128B/130B, 128B/132B, binary, hex
PCIe, USB, SATA
64/80/130/132 bit
Yes ⁵
Capture on event. Capture n bit before/after event:
–– User defined (minimum) amount of pre-event bits/ symbols and minimum
capture bit/symbols
–– Events: error, CTRL IN A/B, immediate
–– Max 2 Gbit/ch capture data
Save captured data:
–– With errors
–– As expected data (ignores error content)
–– As PG data (ignores error content)
–– Export via pattern editor windows
–– Export captured data, displays bit & symbol errors
–– Convert bits into all other codings and vice versa
–– Ability to mask error bits automatically
Display of captured data:
–– Display errors with color coding
–– Navigate through error bits/symbols (find next/previous)
3 counted loop levels, 1 infinite loop, # of blocks: 500
M8041A M8051A M8061A M8062A
x
x
x
x
Opt. 0S1 N/A
No
No
x
x
No
No
x
x
No
No
x
x
*2
*2
x
x
N/A
No
x
x
x
x
1.  Note: polarity is inverted compared to ParBERT and J-BERT N4903A/B and N49xx models.
2.  For availability: contact factory. Free software update.
3.  Modified compliance pattern for PCIe3.
4.  Requires M8070A software revision 1.5.0.0 or later. Free upgrade (interactive link training requires option 0S1).
5.  Requires M8070A software revision 2.0.0.0 or later.