N5106A Datasheet, PDF (13/16 Pages) Keysight Technologies – PXB Baseband Generator and Channel Emulator

General Chassis
Characteristics
continued...
System clock rear panel connectors
EXT I/O CLK IN
EXT SYNC
EXT TRIG IN
EXT REF IN
10 MHz OUT
100 MHz SYS CLK OUT
I/O CLK OUT
TRIGGER OUT
AUX I/O
Reserved for future use
Reserved for future use
External trigger signal used to trigger the start of
the FPGA process 3.3 V CMOS [male SMB]
Damage level: < 0 V and > 3.3 V
Input for an external frequency reference signal
1 MHz to 100 MHz, –5 to + 10 dBm; 50 Ω [male SMB]
Lock range: ±5 ppm
Damage level: < 0 V and > 3.3 V
10 MHz reference output used to lock the frequency
reference of other test equipment to the PXB
900 mVpp; 50 Ω [male SMB]
Damage level: < 0 V and > 3.3 V
100 MHz system clock output
2 Vpp; 50 Ω [male SMB]
Damage level: < 0 V and > 3.3 V
Reserved for future use
Routed from hardware or software trigger input TTL;
100 Ω [male SMB]
Damage level: < 0.5 V and > 5.5 V
Provides additional digital signal interface and feedback
3.3 V CMOS [male 20 pin mini delta]
Damage level: < 0 V and > 3.3 V
CPU host controller rear panel connectors
MONITOR
USB SLAVE (top)
USB MASTER (top)
LAN
VGA connection of an external monitor
Standard USB 2.0 ports, Type A connect to
external peripherals such as a mouse, keyboard,
printer, DVD drive, or hard drive
USB 2.0 port, Type B USB TMC (test and
measurement class) connects to an external PC
controller to control the PXB and for data
transfers over a 480 Mbps link
Network interface used to control the PXB remotely
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