M3302A Datasheet, PDF (13/19 Pages) Keysight Technologies – PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming

13 | Keysight | M3302A PXIe Arbitrary Waveform Generator and Digitizer Combo with Optional Real-Time Sequencing and FPGA Programming - Data Sheet
AC performance
Parameter
General specifications
Analog output jitter
AWG trigger to output jitter
Trigger resolution
Channel-to-channel skew
Clock output jitter
Clock accuracy and stability
AC specifications
Spurious-free dynamic range (SFDR)
f_out = 10 MHz
f_out = 80 MHz
f_out = 120 MHz
f_out = 160 MHz
Crosstalk (adjacent channels)
f_out = 10 MHz
f_out = 80 MHz
f_out = 120 MHz
f_out = 160 MHz
Crosstalk (non-adjacent channels)
f_out = 10 MHz
f_out = 80 MHz
f_out = 120 MHz
f_out = 160 MHz
Phase noise (SSB)
offset = 1 KHz
offset = 10 KHz
offset = 100 KHz
Average noise power density
M3302A-C22
Min
Typ
Max
<2
<2
10
< 20
< 50
< 150
<2
100
70
64
65
63
< –105
–75
–88
–73
< –105
–78
< –105
–92
< –127
< –133
< –138
< –145
Units Comments
ps
RMS (cycle-to-cycle)
ps
RMS (cycle-to-cycle) for any trigger referenced to the chassis clock;
independent of input trigger jitter if input jitter < 4nS peak-to-peak
ns
ps
Between ch 0 & ch 1, and ch 2 & ch 3
ps
Between any channel
ps
Between modules, chassis dependant²
ps
RMS (cycle-to-cycle)
ppm
PXIe, cPCIe versions; chassis dependent¹.
P_out = 4 dBm, measured from DC to max frequency
dBc
dBc
dBc
dBc
dB
dB
dB
dB
dB
dB
dB
dB
dBc/Hz
dBc/Hz
dBc/Hz
dBm/Hz
1.  This value corresponds to a M9505A chassis. This value can be improved with an external chassis clock or a system timing module.
2.  This value corresponds to a M9005A PXIe chassis.
Table 10. AC performance