W2307EP Datasheet, PDF (1/2 Pages) Keysight Technologies – Controlled Impedance Line Designer

Keysight W2307EP/ET
Controlled Impedance Line Designer (CILD)
Data Sheet
Controlled Impedance Line Designer lets you optimize your PCB stack up and transmis-
sion line geometry using metrics that matter, namely post-equalizer eye diagram param-
eters. Other tools will show you the impairments of the lines, such as loss, frequency roll
off, and impedance variation, but in today’s multi gigabit chip to chip links these metrics
are inadequate. What really matters is the eye parameters after the line impairments
have been mitigated by the signal processing in modern SerDes, for example Tx pre-em-
phasis and Rx equalization. In fact the whole point of the signal processing in the I/O of
modern chips is to allow you to use lower cost materials and yet still open the eye.
Controlled Impedance line Designer achieves this by letting you place a Tx and Rx around
the candidate line to form a complete ADS Channel Simulator or ADS Transient Simulator
schematic. In particular, the statistical mode of Channel Simulator can yield ultra low
BER contours in seconds per point in the design space. You can quickly sweep parame-
ters like width and spacing to see the effect.
Key Features
–– Create a pre-layout channel in an
end-to-end ADS Channel Simula-
tor schematic
–– Optimize the metrics that matter
–– Eye Diagram parameters in-
cluding mitigation
–– Bode plots of the channel
impairment
–– Design the stack up and line ge-
ometry of the controlled imped-
ance lines
–– Determine the parameters that you
feed into the Constraint Manager
of the auto-router in your enter-
prise PCB tool
Requirements
–– OS platform support: Linux 64-bit
Windows 64-bit
–– W2200 ADS Core
–– W2302 ADS Transient Convolution
Simulator Element : only required if
line is to be evaluated in a end-to-
end simulation