IRFZ24N Datasheet, PDF (4/8 Pages) NXP Semiconductors – N-channel enhancement mode TrenchMOS transistor

700
V _GS = 0V,
f = 1MHz
C _iss = C _gs + C _gd , C_ds S H O R TE D
600
C _rss = C _gd
C _oss = C _ds + C _gd
500
C iss
400
C oss
300
200
C rss
100
0
A
1
10
100
V _DS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
T_J = 175°C
T_J = 25 °C
10
1
VGS = 0V _A
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
V_SD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
IRFZ24N
20
I_D = 10A
16
V _DS = 44V
V _DS = 28V
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
A
0
4
8
12
16
20
Q _G , Total Gate Charge (nC)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
OPERATION IN THIS AREA LIMITED
BY R DS(on)
100
10µs
10
100µs
T_C = 25°C
T_J = 175°C
S ing le P u lse
1
1
10
1ms
10ms
A
100
V_DS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
2014-8-9
4
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