C1632C103K5RAC Datasheet, PDF (1/7 Pages) Kemet Corporation – Four individual capacitors inside one 1206 monolithic structure

CERAMIC CAPACITOR ARRAY
FEATURES
• Four individual capacitors inside
one 1206 monolithic structure
• Saves board and inventory space
• One placement instead of four - less costly
• Easier to handle and solder than 4 smaller chips
• Tape and reel per EIA 481-1
• RoHS Compliant
CAPACITOR OUTLINE DRAWING
BW
W
L
CL
P
P/2
Ref
T
BW1
TABLE 1
EIA DIMENSIONS – MILLIMETERS (INCHES)
Size
Code
Length
L
Width
W
Thickness
T (max.)
Bandwidth Bandwidth
BW
BW1
Pitch
P
1632 3.2 (0.126) 1.6 (.063)
0.7 - 1.35
0.40 (0.016)
0.1 - 0.5
0.8 (0.031)
± 0.2 (0.008) ± 0.2 (.008) (0.027 - 0.053) ± 0.2 (0.008) (0.004 - 0.020) ± 0.1 (0.004)
Notes:
1. Metric is controlling - English for reference only.
2. Pitch (P) tolerances are non-cumulative along the package.
3. Thickness (T) depends on capacitance.
CERAMIC ARRAY ORDERING INFORMATION
C 1632 C 103 K 5 R A C
CERAMIC
EIA SIZE CODE
Ceramic chip array
SPECIFICATION
C - Standard
CAPACITANCE CODE
Expressed in Picofarads (pF)
First two digits represent significant figures.
Third digit specifies number of zeros. (Use 9
for 1.0 thru 9.9pF. (Example: 2.2pF = 229
CAPACITANCE TOLERANCE
K – ±10%: M – ±20% Standard Tolerances
Contact factory for any special requirements.
END METALLIZATION
C-Standard
(Tin-plated nickel barrier)
FAILURE RATE LEVEL
A- Not Applicable
TEMPERATURE CHARACTERISTIC
Designated by Capacitance
Change Over Temperature Range
G – C0G (NP0) (±30 PPM/°C)
R – X7R (±15%)
VOLTAGE
5 = 50v; 3 = 25v; 4 = 16v; 8=10v
©KEMET Electronics Corporation, P.O. Box 5928, Greenville, S.C. 29606, [phone]
85