843S1333D Datasheet, PDF (10/15 Pages) Integrated Device Technology – Crystal-to-3.3V LVPECL Clock Synthesizer

843S1333D Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 843S1333D.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 843S1333D is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V_CC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
The maximum current at 70°C is as follows: I_{DD_MAX} = 77.68mA
• Power (core)_MAX = V_{CC_MAX} * I_{EE_MAX} = 3.465V * 77.68mA = 269.16mW
• Power (outputs)_MAX = 32mW/Loaded Output pair
Total Power__MAX (3.3V, with all outputs switching) = 269.16mW + 32mW = 301.16mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = _JA * Pd_total + T_A
Tj = Junction Temperature
_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 115.2°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.301W * 115.2°C/W = 104.7°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (single layer or multi-layer).
Table 7. Thermal Resistance _JA for 8 Lead TSSOP, Forced Convection
_JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
115.2°C/W
1
110.9°C/W
2.5
108.8°C/W
©2015 Integrated Device Technology, Inc
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Revision A December 2, 2015