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821024_14 Datasheet, PDF (1/14 Pages) Integrated Device Technology – QUAD NON-PROGRAMMABLE PCM CODEC | |||
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QUAD NON-PROGRAMMABLE
PCM CODEC
821024
DATASHEET
FEATURES
⢠4 channel CODEC with on-chip digital ï¬lters
⢠Selectable A-law or μ-law companding
⢠Master clock frequency selection: 2.048 MHz, 4.096 MHz or
8.192 MHz
- Internal timing automatically adjusted based on MCLK and frame
sync signal
⢠Separate PCM and master clocks
⢠Single PCM port with up to 8.192 MHz data rate (128 time slots)
⢠Transhybrid balance impedance hardware adjustable via external
components
⢠Transmit gains hardware adjustable via external components
⢠Low power +5.0 V CMOS technology
⢠+5.0 V single power supply
⢠Package available: 32 pin PLCC, 44 pin TQFP
DESCRIPTION
The IDT821024 is a single-chip, four channel PCM CODEC with on-
chip ï¬lters. The device provides analog-to-digital and digital-to-analog
conversions and supports both a-law and μâlaw companding. The digital
ï¬lters in IDT821024 provides the necessary transmit and receive ï¬ltering for
voice telephone circuit to interface with time-division multiplexed systems.
All of the digital ï¬lters are performed in digital signal processors operating
from an internal clock, which is derived from MCLK. The ï¬xed ï¬lters set
the transmit and receive gain and frequency response.
In the IDT821024 the PCM data is transmitted to and received from the
PCM highway in time slots determined by the individual Frame Sync signals
(FSRn and FSXn, where n = 1-4) at rates from 256 KHz to 8.192 MHz. Both
Long and Short Frame Sync modes are available in the IDT821024.
The IDT821024 can be used in digital telecommunication applications
such as PBX, Central Ofï¬ce Switch, Digital Telephone and Integrated
Voice/Data Access Unit.
FUNCTIONAL BLOCK DIAGRAM
821024 REVISION A JUNE 25, 2014
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©2014 Integrated Device Technology, Inc.
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