CPC5712 Datasheet, PDF (8/11 Pages) Clare, Inc. – Phone Line Monitor with Detectors (PLMD)

INTEGRATED CIRCUITS DIVISION
3.1 Line Interface
Between the CPC5712 and the TIP/RING line is a
high impedance resistive divider network that provides
sufficient impedance to meet the barrier insulation
specifications in safety regulations and comply with
the on-hook DC leakage to ground requirements from
the various network compatibility specifications.
To ensure regulatory compliance, a 20M or greater
resistance is required from the individual TIP and
RING leads to the IN+ and IN- inputs. For most
applications where the tip and ring interface does not
have a ground referenced surge protector, Clare
recommends using two 1206-size 10M resistors in
series to provide the minimum impedance and to meet
surge requirements. Resistors having a smaller
physical footprint may be used when ground
referenced surge protection is available.
In practice, each 1206-size resistor is capable of
withstanding the 2000V peak waveforms typical of
lightning surges on the phone line. Hence, two 1206
resistors can withstand 4000V lightning pulses.
3.2 Differential Input Resistor
The differential input resistor placed across the IN+
and IN- inputs provides two functions.
From the application perspective, this component
provides a scaled down representation of the tip and
ring line voltage to the CPC5712 inputs. The voltage
applied to the inputs is easily calculated because it is
derived from a simple resistive divider comprising the
tip and ring input resistors and the differential input
resistor.
For improved performance, the CPC5712 signal path
is trimmed at the factory to reduce comparator
detection errors caused by offset currents and
voltages. The CPC5712’s input offset effects are
reduced by trimming the device with an 806kinput
resistor. Using any other value resistor at the inputs
negates the trim and introduces offset errors.
CPC5712
3.3 Voltage Detector Design
From the application requirements given above, the
desired LIU detector threshold voltages are therefore:
• V_H2 = 15V
• V_L2 = 12V
and the detector thresholds for the LOOP detector are:
• V_H1 = 5V
• V_L1 = 3V
3.3.1 Calculate Resistor Values
From the design equations provided in
Section 2.5 “Detector Threshold Operation” on
page 6 this gives:
• R1=R1
• R2=0.666667 R1
• R3=2.333333 R1
• R4=R1
• R5=5.125558 R1
Summing these equations provides the following
result:
R1+R2+R3+R4+R5 = 10.12556 R1
and since this sum is bound by:
20k < (R1 + R2 + R3 + R4 + R5) < 1M
this reduces to: 20k < (10.12556 R1) < 1M
Taking into account the additional constraint of resistor
tolerance, 1% in this example, the range of allowable
values for R1 is further reduced and becomes:
1.995k < R1 < 97.782k permitting a value
for R1 to be chosen.
Selecting a standard value from the E96, 1% table for
R1 of 26.7k the calculated values for the remaining
resistors becomes:
• R2=17.8k
• R3=62.3k
• R4=26.7k
• R5=136.85k
Since the calculated values of R3 and R5 are not
standard values, a reasonable compromise for these
resistors is: R3=61.9k, R5=137k. See Figure 1.
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