IX9907N Datasheet, PDF (7/10 Pages) IXYS Corporation – Single stage, primary control with PFC and dimming

INTEGRATED CIRCUITS DIVISION
IX9907
2.2 Normal Operation
Because the IX9907 employs quasi-resonant
operation, its PWM switch-on is set by the zero
crossing of the auxiliary winding voltage, and the
switch-off is set by the current sense voltage.
is 42s nominal. Turn-on of the power switch cannot
occur during the suppression time, but does occur
after a zero-crossing is detected. In the case of a
missed zero-crossing, a maximum off-time is
implemented. After the power switch has been off for
42s nominal (t_offMax), it is turned back on.
2.2.1 Zero Crossing & Switch-On Determination
2.2.2 Switch-Off Determination
The application example in Figure 1 shows that the
voltage from the auxiliary winding is connected to the
zero crossing pin, ZCV, through an RC network. This
network provides a delay so that switch-on can occur
at a voltage valley, thus enhancing efficiency. The
required time delay, t, should be approximately
one-fourth of the oscillation period (determined by the
inductance of the transformer’s primary and the
drain-source capacitance of the built-in power switch
MOSFET) minus the propagation delay from
zero-cross detect to power switch-on, t_delay.
t
=
t_{--O----S---C-}
4
–
t_delay
This time delay, t, should be matched by adjusting
the RC network.
t_RC
=
C_ZCV

R_{----Z---C----V---1-}
R_ZCV2
After the power switch is turned off, its V_DS will show
some oscillation. This will also show on the ZCV input.
To avoid a mis-triggered switch turn-on, a ringing
suppression circuit is implemented. The suppression
time has two values that depend on the voltage at
ZCV. If V_ZCV is greater than 0.7V, then the time is
2.5s nominal. If V_ZCV is less than 0.7V, then the time
In the application circuit the primary current is sensed
by R_CS. The voltage across this resistor, V_CS, is
applied to the CS input of the device. It is processed
internally (V_CSINT = V_CS(3) + 0.7V), and compared to
the voltage at the VR pin, which is a scaled version of
the rectified line voltage. When V_CSINT > VR, the
power switch is turned off.
Leading-edge blanking is used to prevent a false
trigger caused by the voltage spike across R_CS at the
moment of power switch turn-on. This blanking time,
t_BLKCS, is nominally 450nS. To prevent transformer
saturation, a maximum on-time circuit is implemented.
Max on-time for the power switch is 30s nominal.
2.2.3 Foldback Point Correction
When the AC line voltage increases, the power switch
on-time decreases, which increases the operating
frequency. As a result, with a constant primary current
limit, the output power increases. To provide output
power regulation with respect to line voltage, the
internal foldback point correction circuit varies the V_CS
limit. The V_CS limit is decreased in response to an
increase in AC line voltage. The relationship between
V_CSMax and V_IN is shown in Figure 3.
Figure 3 V_CSMax vs. V_IN
Variation of V_CS Limit Voltage
With Respect to V_IN
1.1
1.0
0.9
0.8
0.7
0.6
50
100 150 200 250 300 350 400 450
V_IN (V)
R02
www.ixysic.com
7