NCD2100 Datasheet, PDF (6/20 Pages) IXYS Corporation – Wide capacitance range of 6.6pF to 37.553pF

INTEGRATED CIRCUITS DIVISION
NCD2100
1.9 Digital Interface Electrical Characteristics
Parameter
Input Voltage
Logic 1 Threshold
Logic 0 Threshold
Hysteresis
Output Voltage
Logic 1
Logic 0
Pull-Down Resistors
Pins CLK and DA
Pin PV
Input Capacitance
Conditions
Symbol Minimum Typical Maximum Unit
CLK and DA
V_IH
-
CLK, DA and PV
V_IL
0.5
CLK and DA
V_IH - V_IL
-
-
V_DD-0.5
-
-
V
0.2
-
Pin PV
with a 68k
Pull-up to V_DD
V_OH
0.6 V_DD
V_OL
V
0.4 V_DD
T_A = +25C
118
135
150
T_A = 25 ±5C
R_CLK, R_DA
116
154
k
-40C < T_A < +85C
101
184
T_A = +25C
157
180
203
T_A = 25 ±5C
R_PV
155
205
k
-40C < T_A < +85C
135
245
CLK and DA
C_CLK, C_DA
-
-
1.2
pF
1.10 Digital Interface AC Characteristics
Parameter
Conditions
Symbol Minimum Typical Maximum Unit
Serial Clock
Frequency
Duty Cycle
-
f_CLK
-
D_CLK
40
-
120
kHz
50
60
%
Serial Data
Setup time
Hold time
-
t_setup
1
-
-
us
t_hold
1
-
-
us
Shift Register Mode
X1 Valid delay
CLK = 1
t_{d_X1}
-
-
1
us
Programming Mode
V_DD = 5V, T_A = 25 + 5C
PV Rising Edge delay
CLK = 1
t_{d_PV}
4
-
-
us
PV Pulse Width
V_PV = 6.5V
t_PV
40
-
80
us
CLK Falling Edge delay
PV = 0
t_{d_CLK}
0
-
-
us
X1 Valid delay
CLK = 0
t_{d_M-X1}
-
-
15
us
Programming Verification
V_DD = 5V,
Only one input bit = logic 0
PV Output Voltage Valid delay
CLK = 1
t_{d_PV_out}
-
-
4
us
Power Up Delay: Time before sending the first
command after power supply reaches 95% of its value.
-
t_SC
500
-
-
s
6
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