IXLD02SI Datasheet, PDF (5/6 Pages) IXYS Corporation – Differential 2A Ultra Fast Laser Diode Driver

Figure 2 - Programmed I_OUT pulse width, t_PW as a function of I_IPW and I_IBI
IXLD02SI
Figure 2 is an illustration of the pulse width vs. programming current. The programming current is typically a DC
level, however it could just as well be a time varying signal. The bandwidth of this portion of the IXLD02 is equivalent
to the maximum operating frequency of 17MHz. For the fastest response time this pin should be driven from a low
source impedance.
Figure 3 - Control Gate Timing Diagram
Figure 3 is a timing chart for the IXLD02. The proper gating of the IXLD02 is extremely important. The device is
capable of 2A of current and may consume in excess of 3A during the pulse. If the supply voltage is at 7V with 3A of
current, the total power dissipated is 21W. Therefore ample heat sinking must be provided, and/or the duty cycle
must be limited so that the power dissipation capability of the device is not exceeded.
The Power Up Gate (PDN) is applied to activate the device. Time interval “A” can be >30ns. At the end of this time
period the control gate “B” (FIN), can be applied. The range of “B” is from 1ns to several µs. The maximum frequency
1/C is approximately 17MHz.
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