CPC3701 Datasheet, PDF (3/5 Pages) Clare, Inc. – Vertical DMOS FET

INTEGRATED CIRCUITS DIVISION
CPC3701
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.0
PERFORMANCE DATA* @ 25ºC (Unless Otherwise Noted)
Output Characteristics
V_GS=0V
V_GS=-0.5V
V_GS=-1V
V_GS=-1.5V
V_GS=-2V
V_GS=-2.5V
V_GS=-3V
0.5
1.0
1.5
2.0
2.5
V_DS (V)
Threshold Voltage vs. Temperature
-2.05
(I_DS=1PA)
-2.10
-2.15
-2.20
-2.25
-2.30
-2.35
-2.40
-40 -20
0 20 40 60
Temperature (ºC)
80 100
Forward Safe Operating Bias
(V_GS=0V)
1
0.1
0.01
0.01
0.1
1
10
100
Voltage (V)
Power Dissipation vs. Temperature
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
20 40 60 80 100 120 140
Temperature (ºC)
Capacitance vs. Drain-Source Voltage
(V_GS=-5V)
500
400
CISS
300
200
100
0
0
COSS
10
20
30
40
50
V_DS (V)
Leakage Current (I_DS) vs. Temperature
(V_GS=-5V, V_DS=60V)
120
100
80
60
40
20
0
-40 -20
0 20 40 60
Temperature (ºC)
80 100
Breakdown Voltage (V_DS) vs. Temperature
(V_GS=-5V, I_DS=10PA)
82
80
78
76
74
72
-40 -20
0 20 40 60
Temperature (ºC)
80 100
*The Performance data shown in the graphs above is typical of device performance. For guaranteed parameters not indicated in the written specifications, please
contact our application department.
R06
www.ixysic.com
3