IXTR30N25 Datasheet, PDF (1/2 Pages) IXYS Corporation – N-Channel Enhancement Mode

Advance Technical Information
Standard Power MOSFETs
ISOPLUS247^TM
(Electrically Isolated Backside)
IXTR 30N25
V_DSS =
I_{D (cont)} =
R_DS(on) =
250 V
25 A
75 mΩ
N-Channel Enhancement Mode
Avalanche Rated, High dv/dt
Symbol
V_DSS
V
DGR
V_GS
V
GSM
I_D25
I
DM
I_AR
E_AR
E
AS
dv/dt
P
D
T_J
T_JM
T_stg
T_L
V
ISOL
Weight
Symbol
V_DSS
V_GS(th)
I_GSS
I_DSS
R
DS(on)
Test Conditions
T_J = 25°C to 150°C
T_J = 25°C to 150°C; R_GS = 1 MΩ
Continuous
Transient
T_C = 25°C
T_C = 25°C, Note 1
T_C = 25°C
T_C = 25°C
T_C = 25°C
I_S ≤ I_DM, di/dt ≤ 100 A/µs, V_DD ≤ V_DSS
T_J ≤ 150°C, R_G = 2 Ω
T_C = 25°C
1.6 mm (0.063 in.) from case for 10 s
50/60 Hz, RMS t = 1 min
Maximum Ratings
250
V
250
V
±20
V
±30
V
25
A
120
A
30
A
30
mJ
1.0
J
5 V/ns
150
W
-55 ... +150
°C
150
°C
-55 ... +150
°C
300
°C
2500
V~
5
g
Test Conditions
V_GS = 0 V, I_D = 250µA
V_DS = V_GS, I_D = 250µA
V_GS = ±20 V, V_DS = 0
V_DS = V_DSS
V_GS = 0 V
V_GS = 10 V, I_D = I_T
Notes 2, 3
Characteristic Values
(T_J = 25°C, unless otherwise specified)
min. typ. max.
250
2.0
T_J = 125°C
60
V
4.0 V
±100 nA
25 µA
250 µA
75 mΩ
ISOPLUS 247^TM
E153432
Isolated backside*
G = Gate
D = Drain
S = Source
* Patent pending
Features
l _{Silicon chip on Direct-Copper-Bond}
substrate
- High power dissipation
- Isolated mounting surface
- 2500V electrical isolation
l _{Low drain to tab capacitance(<30pF)}
l _{Low RDS (on) HDMOS}TM _process
l _{Rugged polysilicon gate cell structure}
l _{Rated for Unclamped Inductive Load}
Switching (UIS)
Applications
l _{DC-DC converters}
l _{Battery chargers}
l _{Switched-mode and resonant-mode}
power supplies
l _{DC choppers}
l _{AC motor control}
Advantages
l _{Easy assembly}
l _{Space savings}
l _{High power density}
© 2001 IXYS All rights reserved
98873 (12/01)