IXTH41N25 Datasheet, PDF (1/4 Pages) IXYS Corporation – N-Channel Enhancement Mode

Standard
Power MOSFET
N-Channel Enhancement Mode
Preliminary Data Sheet
IXTH 41N25
V_DSS =
I_D(cont) =
= R_DS(on)
250 V
41 A
72 mΩ
Symbol Test conditions
V_DSS
V_DGR
T_J = 25°C to 150°C
T_J = 25°C to 150°C; R_GS = 1.0 MΩ
V_GS
V_GSM
Continuous
Transient
I_D25
I_DM
TT_CC
= 25°C MOSFET chip capability
= 25°C, pulse width limited by T_JM
I_AR
E_AR
E_AS
dv/dt
T_C = 25°C
T_C = 25°C
I_S ≤ I_DM, di/dt ≤ 100 A/µs, V_DD ≤ V_DSS
T_J ≤ 150°C, R_G = 2 Ω
P_D
T_C = 25°C
T_J
T_JM
T_stg
M_d
Weight
Mounting torque
TO-264
Maximum lead temperature for soldering
1.6 mm (0.062 in.) from case for 10 s
Symbol Test Conditions
(T_J = 25°C unless otherwise specified)
V_DSS
V_GS(th)
VV_GDSS
=
=
0 V,
V_GS,
II^DD
=
=
250
250
µA
µA
I_GSS
V_GS = ±20 V DC, V_DS = 0
I_DSS
V_DS = V_DSS
V_GS = 0 V
T_J = 125°C
R_DS(on)
VPu_{GSlse=te1s0t,Vt,≤}I_{D3=0015mAs, duty cycle d ≤ 2%}
Maximum ratings
250
V
250
V
±20
V
±30
V
41
A
164
A
41
A
30
mJ
1.0
J
5
V/ns
300
W
-55 ... +150
°C
150
°C
-55 ... +150
°C
1.13/10 Nm/lb.in.
6
g
300
°C
Characteristic Values
Min. Typ.
Max.
250
V
2.0
4.0 V
±100 nA
25 µA
250 µA
60
72 mΩ
TO-247 AD
GD_S
D (TAB)
G = Gate
S = Source
D = Drain
Tab = Drain
Features
•Low R_{DS (on)} HDMOS^TM process
•Rugged polysilicon gate cell structure
•International standard package
JEDEC TO-247 AD
•Fast switching times
•High commutating dv/dt rating
Applications
• Motor controls
• DC choppers
• Switched-mode and resonant-mode
power supplies
•Uninterruptible Power Supplies (UPS)
Advantages
• Easy to mount with one screw
(isolated mounting screw hole)
• Space savings
• High power density
© 2003 IXYS All rights reserved
DS98954B(08/03)