IXTC13N50 Datasheet, PDF (1/2 Pages) IXYS Corporation – Power MOSFET ISOPLUS220

ADVANCE TECHNICAL INFORMATION
Power MOSFET
ISOPLUS220^TM
IXTC 13N50
Electrically Isolated Back Surface
N-Channel Enhancement Mode
High dv/dt, Low t_rr, HDMOS^TM Family
V_DSS = 500 V
I_D25 = 12 A
R_DS(on) = 0.4 Ω
Symbol
V_DSS
V
DGR
V_GS
V_GSM
I_D25
I_DM
I
AR
E_AR
dv/dt
P_D
T
J
T_JM
T
stg
T_L
Weight
Symbol
V_DSS
V
GS(th)
I
GSS
I_DSS
R
DS(on)
ISOPLUS 220^TM
Test Conditions
T_J = 25°C to 150°C
T_J = 25°C to 150°C; R_GS = 1 MΩ
Continuous
Transient
T_C = 25°C
T_C = 25°C, pulse width limited by T_JM
T_C = 25°C
T_C = 25°C
I_S ≤ I_DM, di/dt ≤ 100 A/µs, V_DD ≤ V_DSS,
T_J ≤ 150°C, R_G = 2 Ω
T_C = 25°C
1.6 mm (0.062 in.) from case for 10 s
Maximum Ratings
500
V
500
V
±20
V
±30
V
12
A
48
A
13
A
18
mJ
5 V/ns
140
W
-55 ... +150
°C
150
°C
-55 ... +150
°C
300
°C
3
g
Test Conditions
V_GS = 0 V, I_D = 250 µA
V_DS = V_GS, I_D = 2.5 mA
V_GS = ±20 V_DC, V_DS = 0
V_DS = 0.8 V_DSS
V_GS = 0 V
V_GS = 10 V, I_D = I_T
Notes 1, 2
Characteristic Values
(T_J = 25°C, unless otherwise specified)
min. typ. max.
500
2
T_J = 25°C
T_J = 125°C
V
4V
±100 nA
200 µA
1 mA
0.4 Ω
G
D
S
Isolated back surface*
G = Gate,
S = Source
D = Drain,
* Patent pending
Features
l _{Silicon chip on Direct-Copper-Bond}
substrate
- High power dissipation
- Isolated mounting surface
- 2500V electrical isolation
l _{Lowdraintotabcapacitance(<35pF)}
l _{Low RDS (on) HDMOS}TM _process
l _{Ruggedpolysilicongatecellstructure}
l _{UnclampedInductiveSwitching(UIS)}
rated
Applications
l _{DC-DC converters}
l _{Batterychargers}
l _{Switched-modeandresonant-mode}
power supplies
l _{DC choppers}
l _{AC motor control}
Advantages
l _{Easy assembly: no screws or isolation}
foils required
l _{Space savings}
l _{High power density}
l _{Lowcollectorcapacitancetoground}
(low EMI)
© 2001 IXYS All rights reserved
98823 (05/01)