IXFR4N100Q Datasheet, PDF (1/2 Pages) IXYS Corporation – HiPerFET Power MOSFETs ISOPLUS247 (Electrically Isolated Backside)

HiPerFET^TM Power MOSFETs
ISOPLUS247^TM
(Electrically Isolated Backside)
N-Channel Enhancement Mode
Avalanche Rated, Low Q_g, High dv/dt
Preliminary Data
IXFR 4N100Q
V_DSS = 1000 V
I
= 3.5 A
D25
R_DS(on) = 3.0 Ω
t_rr ≤ 200ns
Symbol
V_DSS
V
DGR
V_GS
V
GSM
I_D25
I
DM
I_AR
E_AR
E
AS
dv/dt
P
D
T_J
T_JM
T_stg
T_L
V
ISOL
Weight
Symbol
V_DSS
V_GS(th)
I_GSS
I_DSS
R_DS(on)
Test Conditions
T_J = 25°C to 150°C
T
J
=
25°C
to
150°C;
R
GS
=
1
MΩ
Continuous
Transient
T_C = 25°C
T
C
= 25°C, Note 1
T_C = 25°C
T_C = 25°C
T
C
=
25°C
I_S ≤ I_DM, di/dt ≤ 100 A/µs, V_DD ≤ V_DSS
T
J
≤
150°C,
R
G
=
2
Ω
T
C
=
25°C
1.6 mm (0.063 in.) from case for 10 s
50/60 Hz, RMS t = 1 min
Maximum Ratings
1000
1000
±20
±30
3.5
16
4
20
700
5
V
V
V
V
A
A
A
mJ
mJ
V/ns
80
W
-55 ... +150
°C
150
°C
-55 ... +150
°C
300
°C
2500
V~
5
g
Test Conditions
V_GS = 0 V, I_D = 1mA
V_DS = V_GS, I_D = 1.5 mA
V_GS = ±20 V_DC, V_DS = 0
V_DS = V_DSS
V =0V
GS
V_GS = 10 V, I_D = I_T
Notes 2, 3
Characteristic Values
(T_J = 25°C, unless otherwise specified)
min. typ. max.
1000
V
3.0
5.0 V
±100 nA
T_J = 25°C
T
J
= 125°C
50 µA
1 mA
3.0 Ω
ISOPLUS 247^TM
E153432
Isolated backside*
G = Gate
S = Source
D = Drain
* Patent pending
Features
z _{Silicon chip on Direct-Copper-Bond}
substrate
- High power dissipation
- Isolated mounting surface
- 2500V electrical isolation
z _{Low drain to tab capacitance(<30pF)}
z _{Low RDS (on) HDMOS}TM _process
z _{Rugged polysilicon gate cell structure}
z _{Rated for Unclamped Inductive Load}
Switching (UIS)
z _{Fast intrinsic Rectifier}
Applications
z _{DC-DC converters}
z _{Battery chargers}
z _{Switched-mode and resonant-mode}
power supplies
z _{DC choppers}
z _{AC motor control}
Advantages
z _{Easy assembly}
z _{Space savings}
z _{High power density}
© 2002 IXYS All rights reserved
DS98860A(12/02)