IXFR21N100Q_03 Datasheet, PDF (1/4 Pages) IXYS Corporation – HiPerFET Power MOSFETs ISOPLUS247

HiPerFET^TM Power MOSFETs
ISOPLUS247^TM
IXFR 21N100Q
(Electrically Isolated Back Surface)
N-Channel Enhancement Mode, Low Q_g,
High dv/dt, Low t_rr, HDMOS^TM Family
V_DSS
I_D25
R_DS(on)
= 1000 V
= 18 A
= 0.50 Ω
t_rr ≤ 250 ns
Symbol
V_DSS
V_DGR
V_GS
V_GSM
I_D25
I_DM
I_AR
E_AR
E_AS
dv/dt
P_D
T_J
T_JM
T_stg
T_L
V_ISOL
Weight
Symbol
V_DSS
V_GS(th)
I_GSS
I_DSS
R_DS(on)
Test Conditions
T_J = 25°C to 150°C
T_J = 25°C to 150°C; R_GS = 1 MΩ
Continuous
Transient
T_C = 25°C
T_C = 25°C, Note 1
T_C = 25°C
T_C = 25°C
T_C = 25°C
I_S ≤ I_DM, di/dt ≤ 100 A/µs, V_DD ≤ V_DSS
T_J ≤ 150°C, R_G = 2 Ω
T_C = 25°C
1.6 mm (0.063 in.) from case for 10 s
50/60 Hz, RMS t = 1 min
Maximum Ratings
1000
1000
±20
±30
18
84
21
60
2.5
10
V
V
V
V
A
A
A
mJ
J
V/ns
350
W
-55 ... +150
°C
150
°C
-55 ... +150
°C
300
°C
2500
V~
5
g
Test Conditions
V_GS = 0 V, I_D = 1mA
V_DS = V_GS, I_D = 4mA
V_GS = ±20 V, V_DS = 0
V_DS = V_DSS
V_GS = 0 V
V_GS = 10 V, I_D = I_T
Notes 2, 3
Characteristic Values
(T_J = 25°C, unless otherwise specified)
min. typ. max.
1000
V
3
5V
±100 nA
T_J = 125°C
100 µA
2 mA
0.5 Ω
ISOPLUS 247^TM
E153432
G = Gate
S = Source
Isolated backside*
D = Drain
* Patent pending
Features
z _{Silicon chip on Direct-Copper-Bond}
substrate
- High power dissipation
- Isolated mounting surface
- 2500V electrical isolation
z _{IXYS advanced low Qg process}
z _{Low gate charge and capacitances}
- easier to drive
-faster switching
z _{Low drain to tab capacitance(<30pF)}
z _{Low RDS (on) HDMOS}TM _process
z _{Rugged polysilicon gate cell structure}
z _{Rated for Unclamped Inductive Load}
Switching (UIS)
z _{Fast intrinsic Rectifier}
Applications
z _{DC-DC converters}
z _{Battery chargers}
z _{Switched-mode and resonant-mode}
power supplies
z _{DC choppers}
z _{AC motor control}
Advantages
z _{Easy assembly}
z _{Space savings}
z _{High power density}
© 2003 IXYS All rights reserved
DS98723B(01/03)