IXFJ40N30 Datasheet, PDF (1/2 Pages) IXYS Corporation – HiPerFET Power MOSFETs

HiPerFET^TM
Power MOSFETs
N-Channel Enhancement Mode
High dv/dt, Low t_rr, HDMOS^TM Family
Preliminary data sheet
IXFJ 40N30
V_DSS = 300 V
I_D25 = 40 A
R_DS(on) = 80 mW
t_rr < 200 ns
Symbol
V_DSS
V_DGR
V_GS
V
GSM
I_D25
I_DM
I_AR
E_AR
dv/dt
P_D
T_J
T_JM
T_stg
T_L
Weight
Symbol
V
DSS
V_GS(th)
I_GSS
I
DSS
R_DS(on)
Test Conditions
T_J = 25°C to 150°C
T_J = 25°C to 150°C; R_GS = 1 MW
Continuous
Transient
T_C = 25°C
T_C = 25°C, pulse width limited by T_JM
T_C = 25°C
T_C = 25°C
I_S £ I_DM, di/dt £ 100 A/ms, V_DD £ V_DSS,
T_J £ 150°C, R_G = 2 W
T_C = 25°C
1.6 mm (0.062 in.) from case for 10 s
Maximum Ratings
300
V
300
V
±20
V
±30
V
40
A
160
A
40
A
30
mJ
5 V/ns
300
W
-55 ... +150
°C
150
°C
-55 ... +150
°C
300
°C
5
g
Test Conditions
Characteristic Values
(T_J = 25°C, unless otherwise specified)
min. typ. max.
V
GS
=
0
V,
I
D
=
250
mA
300
V_DS = V_GS, I_D = 4 mA
2
V_GS = ±20 V_DC, V_DS = 0
V = 0.8 • V
DS
DSS
V_GS = 0 V
T
J
=
25°C
T_J = 125°C
V_GS = 10 V, I_D = 0.5 I_D25
Pulse test, t £ 300 ms, duty cycle d £ 2 %
V
4V
±100 nA
200 mA
1 mA
80 mW
G
D
S
é
(TAB)
G = Gate,
S = Source,
D = Drain,
TAB = Drain
Features
• Low profile, high power package
• Long creep and strike distances
• Easy up-grade path for TO-220
designs
• Low R HDMOS^TM process
•
DS (on)
Rugged polysilicon
gate
cell
structure
• Unclamped Inductive Switching (UIS)
rated
• Low package inductance
- easy to drive and to protect
• Fast intrinsic Rectifier
Applications
• DC-DC converters
• Synchronous rectification
• Battery chargers
• Switched-mode and resonant-mode
power supplies
• DC choppers
• AC motor control
• Temperature and lighting controls
• Low voltage relays
Advantages
• High power, low profile package
• Space savings
• High power density
IXYS reserves the right to change limits, test conditions, and dimensions.
© 2000 IXYS All rights reserved
98536 1/99)
1-2