IXFH52N30Q Datasheet, PDF (1/2 Pages) IXYS Corporation – N-Channel Enhancement Mode Avalanche Rated, High dv/dt, Low t Low Gate Charge and Capacitances

HiPerFET^TM
Power MOSFETs
Q-Class
N-Channel Enhancement Mode
Avalanche Rated, High dv/dt, Low t_rr
Low Gate Charge and Capacitances
Preliminary data
IXFH 52N30Q
IXFK 52N30Q
IXFT 52N30Q
V_DSS = 300 V
I_D25 = 52 A
= R_DS(on) 60 mW
t_rr
£ 250 ns
Symbol
V_DSS
V_DGR
V_GS
V_GSM
I
D25
I_DM
I
AR
E_AR
E_AS
dv/dt
P_D
T
J
T_JM
T_stg
T_L
M_d
Weight
Symbol
V
DSS
V_GS(th)
I_GSS
I_DSS
R_DS(on)
Test Conditions
T_J = 25°C to 150°C
T_J = 25°C to 150°C; R_GS = 1 MW
Continuous
Transient
T
C
= 25°C, Chip capability
T_C = 25°C, pulse width limited by T_JM
T
C
= 25°C
T_C = 25°C
T_C = 25°C
I_S £ I_DM, di/dt £ 100 A/ms, V_DD £ V_DSS,
T_J £ 150°C, R_G = 2 W
T_C = 25°C
1.6 mm (0.063 in) from case for 10 s
Mounting torque
TO-247
TO-264
TO-247
TO-264
TO-268
Maximum Ratings
300
V
300
V
±20
V
±30
V
52
A
208
A
52
A
30
mJ
1.5
J
5
V/ns
TO-247 AD (IXFH)
TO-268 (D3) ( IXFT)
G
S
(TAB)
(TAB)
360
W
-55 ... +150
°C
150
°C
-55 ... +150
°C
300
°C
1.13/10 Nm/lb.in.
0.9/6 Nm/lb.in.
6
g
10
g
4
g
TO-264 AA (IXFK)
G
D
S
D (TAB)
G = Gate
S = Source
TAB = Drain
Features
Test Conditions
Characteristic Values
(T_J = 25°C, unless otherwise specified)
min. typ. max.
V = 0 V, I = 1 mA
300
GS
D
V_DS = V_GS, I_D = 4 mA
2
V_GS = ±20 V_DC, V_DS = 0
V_DS = V_DSS
V =0V
GS
T_J = 25°C
T
J
=
125°C
V_GS = 10 V, I_D = 0.5 • I_D25
Pulse test, t £ 300 ms, duty cycle d £ 2 %
V
4V
±200 nA
50 mA
1 mA
60 mW
• Low gate charge
• International standard packages
• EpoxymeetUL94V-0, flammability
classification
• Low R_{DS (on)} HDMOS^TM process
• Rugged polysilicon gate cell structure
• Avalanche energy and current rated
• Fast intrinsic Rectifier
Advantages
• Easy to mount
• Space savings
• High power density
IXYS reserves the right to change limits, test conditions, and dimensions.
© 2000 IXYS All rights reserved
98522B (7/00)
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