IS93C56-3 Datasheet, PDF (9/10 Pages) Integrated Silicon Solution, Inc – 2,048-BIT SERIAL ELECTRICALLY ERASABLE PROM

IS93C56-3
FIGURE 7. WRITE DISABLE (WDS) CYCLE TIMING
tCS
CS
SK
DIN
10
0
00
DOUT = 3-STATE
ISSI ^®
FIGURE 8. ERASE (REGISTER ERASE) CYCLE TIMING
SK
tCS
CS
DIN
1
1
1
X A6
DOUT
X is a don't care bit
A0
tSV
tDF
BUSY
tWP
READY
FIGURE 9. ERASE ALL (ERAL) CYCLE TIMING
SK
tCS
CS
DIN
DOUT
1
00
1
0
tSV
tDF
BUSY
tWP
READY
Note for Figures 8 and 9:
After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status (DOUT
indicates BUSY status) then performs another instruction would cause device malfunction.
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. G
04/26/01