IS61DDB24M18A Datasheet, PDF (9/29 Pages) Integrated Silicon Solution, Inc – Common I/O read and write ports

IS61DDB24M18A
IS61DDB22M36A
State Diagram
Power-Up
NOP
/Load
Load
/LOAD
Load New Read Address
Read
Load
DDR-II Read
Write
Load
DDR-II Write
/LOAD
Notes:
1. Internal burst counter is fixed as two-bit linear; that is, when first address is A0+0, next internal burst address is A0+1.
2. Read refers to read active status with R/W# = High.
3. Write refers to write active status with R/W# = LOW.
4. Load refers to read new address active status with LD# = low.
5. Load is read new address inactive status with LD = high.
Linear Burst Sequence Table
Burst Sequence
First Address
Second Address
Case1
SA₀
0
1
Case2
SA₀
1
0
Integrated Silicon Solution, Inc.- www.issi.com
9
Rev. A
08/15/2014