IS25WP016 Datasheet, PDF (81/112 Pages) Integrated Silicon Solution, Inc – 1.8V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI

ADVANCED INFORMATION
IS25WP016/080/040/020
Figure 8.57 FRQDTR (Fast Read Quad IO DTR Mode) Operation (with command decode cycles)
CE#
SCK
IO0
IO1
IO2
0 1 2 3 4 5 6 7 8 9 10 11 12
Mode 3
Mode 0
Instruction = EDh
High Impedance
6 Dummy Cycles
3-byte Address
20 16 12 8 4 0 4 0
21 17 13 9 5 1 5 1
22 18 14 10 6 2 6 2
IO3
23 19 15 11 7 3 7 3
Mode Bits
CE#
SCK
IO0
IO1
IO2
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Data Data Data Data Data Data Data Data Data Data
t_{V Out Out Out Out Out Out Out Out Out Out}
4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 ^...
5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 ...
6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 ^...
IO3
7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 ^...
Notes:
1. If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the
mode bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.
Integrated Silicon Solution, Inc.- www.issi.com
81
Rev. 00A
01/13/2015