IS61NP25632 Datasheet, PDF (8/20 Pages) Integrated Silicon Solution, Inc – 256K x 32, 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM

IS61NP25632 IS61NP25636 IS61NP51218
IS61NLP25632 IS61NLP25636 IS61NLP51218
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC)
External Address
A1 A0
00
01
10
11
1st Burst Address
A1 A0
01
00
11
10
2nd Burst Address
A1 A0
10
11
00
01
3rd Burst Address
A1 A0
11
10
01
00
ISSI ^®
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS⁽¹⁾
Symbol Parameter
TBIAS
Temperature Under Bias
TSTG
Storage Temperature
PD
Power Dissipation
IOUT
Output Current (per I/O)
VIN, VOUT Voltage Relative to GND for I/O Pins
VIN
Voltage Relative to GND for
for Address and Control Inputs
Value
–10 to +85
–65 to +150
1.6
100
–0.5 to VCCQ + 0.3
–0.3 to 4.6
Unit
°C
°C
W
mA
V
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specifi-
cation is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages or
electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00E
04/26/01