IS42S16400F-7TL-TR Datasheet, PDF (8/55 Pages) Integrated Silicon Solution, Inc – 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

IS42S16400F
IC42S16400F
3. Current state definitions:
Idle: The bank has been precharged, and trp has been met.
Row Active: A row in the bank has been activated, and trcd has been met. No data bursts/accesses and no register
accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi-
nated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi-
nated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands,
or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable com-
mands to the other bank are determined by its current state and CURRENT STATE BANK n truth tables.
Precharging: Starts with registration of a PRECHARGE command and ends when trp is met. Once trp is met, the bank
will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when trcd is met. Once trcd is met, the bank will
be in the row active state.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when trp has been
met. Once trp is met, the bank will be in the idle state.
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when trp has been
met. Once trp is met, the bank will be in the idle state.
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be
applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when trc is met. Once trc is met, the
SDRAM will be in the all banks idle state.
Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when tmrd has been met. Once
tmrd is met, the SDRAM will be in the all banks idle state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when trp is met. Once trp is met, all
banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
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Integrated Silicon Solution, Inc. — www.issi.com
Rev.  A
03/19/08