IS62LV256 Datasheet, PDF (7/9 Pages) Integrated Silicon Solution, Inc – 32K x 8 LOW VOLTAGE STATIC RAM

IS62LV256
ISSI ^®
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2,3) (Over Operating Range)
Symbol
tWC
tSCE
tAW
tHA
tSA
tPWE⁽⁴⁾
tSD
tHD
Parameter
Write Cycle Time
CE to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
-45 ns
Min. Max.
45
—
35
—
25
—
0
—
0
—
25
—
20
—
0
—
-70 ns
Min. Max.
70
—
60
—
60
—
0
—
0
—
55
—
30
—
0
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
4. Tested with OE HIGH.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
Rev. K
12/11/02