IS61C256AL_06 Datasheet, PDF (7/12 Pages) Integrated Silicon Solution, Inc – 32K x 8 HIGH-SPEED CMOS STATIC RAM

IS61C256AL
ISSI ^®
WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) ^(1,2)
ADDRESS
OE
t WC
VALID ADDRESS
t HA
CE ^LOW
WE
DOUT
t SA
DATA UNDEFINED
t AW
t PWE1
t HZWE
DIN
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
CE_WR2.eps
WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) ⁽¹⁾
ADDRESS
OE ^LOW
t WC
VALID ADDRESS
t HA
CE _LOW
WE
DOUT
t SA
DATA UNDEFINED
DIN
t AW
t PWE2
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
CE_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE ≥ VIH.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
Rev. B
10/23/06