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IS43R16320A Datasheet, PDF (7/18 Pages) Integrated Silicon Solution, Inc – 32Meg x 16 512-MBIT DDR SDRAM
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IS43R16320A
ISSI ®
Capacitance
Parameter
Symbol
Min.
Max.
Units
Notes
Input Capacitance: CK, CK
Delta Input Capacitance: CK, CK
Input Capacitance: All other input-only pins (except DM)
Delta Input Capacitance: All other input-only pins (except DM)
Input/Output Capacitance: DQ, DQS, DM
Delta Input/Output Capacitance: DQ, DQS, DM
CI1
2.0
delta CI1
CI2
2.0
delta CI2
CIO
4.0
delta CIO
3.0
0.25
3.0
0.5
5.0
0.5
pF
1
pF
1
pF
1
pF
1
pF
1, 2
pF
1
1. VDDQ = VDD = 2.5V ± 0.2V (minimum range to maximum range), f = 100MHz, TA = 25°C, VODC = VDDQ/2, VOPeak -Peak = 0.2V.
2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is
required to match input propagation times of DQ, DQS and DM in the system.
DC Electrical Characteristics and Operating Conditions
(0°C < TA < 70oC; VDDQ = VDD = + 2.5V ± 0.2V (DDR333); see AC Characteristics)
Symbol
Parameter
Min
Max
Units
Notes
VDD
Supply Voltage DDR 333
VDDQ I/O Supply Voltage DDR333
VSS, VSSQ
Supply Voltage
I/O Supply Voltage
VREF
VTT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VIX(DC)
VIRatio
II
IOZ
I/O Reference Voltage
I/O Termination Voltage (System)
Input High (Logic1) Voltage
Input Low (Logic0) Voltage
Input Voltage Level, CK and CK Inputs
Input Differential Voltage, CK and CK Inputs
Input Crossing Point Voltage, CK and CK Inputs
V-I Matching Pullup Current to Pulldown Current Ratio
Input Leakage Curr ent
Any input 0V < VIN < VDD; (All other pins not under test = 0V)
Output Leakage Current
(DQs are disabled; 0V < Vout < VDDQ
2.3
2.7
V
1
2.3
2.7
V
1
0
0
V
0.49 x VDDQ
0.51 x VDDQ
V
1, 2
VREF - 0.04
VREF + 0.04
V
1, 3
VREF + 0.15 VDDQ + 0.3
V
1
-0.3
VREF - 0.15
V
1
-0.3
VDDQ + 0.3
V
1
0.30
VDDQ + 0.6
V
1, 4
0.30
VDDQ + 0.6
V
1, 4
0.71
1.4
5
-2
2
µA
1
-5
5
µA
1
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak
noise on VREF may not exceed ± 2% of the DC value.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF.
4. VID is the magnitude of the difference between the input level on CK and the input level on CK.
5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and
voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference
between pullup and pulldown drivers due to process variation.
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. A
03/22/06
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