IS25LP128 Datasheet, PDF (68/90 Pages) Integrated Silicon Solution, Inc – 3V SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI

IS25LP032/064/128
Figure 8.53 FRDDTR (Fast Read Dual IO DTR Mode) OPERATION (without command decode cycles)
CE#
SCK
SI
SO
0 1 2 ^... 6 7 8 9 10 11 12 13 14 15 16 ...
Mode 3
Mode 0
2 Dummy Cycles
3-byte Address
t_{V Data Out Data Out Data Out}
22 20 18 16 14 12 10 ^... 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 ^...
Mode Bits
23 21 19 17 15 13 11 ^... 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 ^...
Notes:
1. If the mode bits=AXh (X: don’t care), it can execute the AX read mode (without command). When the mode bits
are different from AXh (X is don’t care), the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.9 Read Dummy Cycles.
3. Since the number of dummy cycles and AX bits cycles are same in the above Figure, X should be Hi-Z to avoid
I/O contention
Integrated Silicon Solution, Inc.- www.issi.com
68
Rev. D
10/03/2014