IS43R16160 Datasheet, PDF (6/37 Pages) Integrated Silicon Solution, Inc – Auto refresh and Self refresh

IS_II_S43₄R_3R16₈1₃6₂0_00B Preliminary
IS43R16160B, IC43R16160B
COMMAND TRUTH TABLE
Zentel Electronics Corporation
A3S56D30/40ETP
256M Double Data Rate Synchronous DRAM
COMMAND
Deselect
No Operation
Row Address Entry &
Bank Activate
Single Bank Precharge
Precharge All Banks
Column Address Entry
& Write
Column Address Entry
& Write with
Auto-Precharge
Column Address Entry
& Read
Column Address Entry
& Read with
Auto-Precharge
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
Burst Terminate
Mode Register Set
MNEMONIC ^{CKE CKE} /CS
n-1 n
DESEL
HXH
NOP
HXL
ACT
HHL
PRE
PREA
HHL
HHL
WRITE
HHL
WRITEA
H
H
L
READ
HHL
READA
REFA
REFS
REFSX
TERM
MRS
HHL
HHL
H
L
L
L
H
H
L
H
L
HHL
HHL
/RAS /CAS /WE BA0,1 ^{A10 A0-9,} note
/AP 11-12
X
X
X
X
X
X
H
H
H
X
X
X
L
H
H
V
V
V
L
H
L
V
L
X
L
H
L
X
H
X
H
L
L
V
L
V
H
L
L
V
H
V
H
L
H
V
L
V
H
L
H
V
H
V
L
L
H
X
X
X
L
L
H
X
X
X
X
X
X
X
X
X
H
H
H
X
X
X
H
H
L
X
X
X1
L
L
L
L
L
V2
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for
read bursts with autoprecharge enabled, and for write bursts.
2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register;BA0=1 ,
BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the
op-code to be written to the selected Mode Register.
6
DDR SDRAM (Rev.1.1)
Integrated Silicon Solution, Inc.
Rev.  00A
09/10/08