IS43DR81280B Datasheet, PDF (6/28 Pages) Integrated Silicon Solution, Inc – 1Gb (x8, x16) DDR2 SDRAM

IS43/46DR81280B/L, IS43/46DR16640B/L
Mode Register (MR) Diagram
Address
Field
BA2
BA1
BA0
A13⁽¹⁾
A12
Mode
Register
0
0
0
0
PD1
A11
A10
WR
A9
A8
DLL
A7
TM
A6
A5
CAS
Latency
A4
A3
BT
A2
A1
Burst
Length
A0
A12 Active power down exit time
0
Fast exit (use tXARD)
1
Slow exit(use tXARDS)
A11 A10 A9 WR(cycles)⁽²⁾
0
0
0
Reserved
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8
A8
DLL Reset
0
No
A7
1
Yes
0
1
A6 A5 A4
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
CAS Latency
Reserved
Reserved
Reserved
3
4
5
6
7
A3
Burst Type
0
Sequential
1
Interleave
Mode
Normal
Reserved
A2 A1 A0 BL
0
1
0
4
0
1
1
8
Notes:
1. A13 is reserved for future use and must be set to 0 when programming the MR.
2. WR(write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min. WR in clock cycles is calculated by dividing tWR (in
ns) by tCK (in ns) and rounding up a non‐integer value to the next integer (WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value.
This is also used with tRP to determine tDAL.
DDR2 Extended Mode Register 1 (EMR[1]) Setting
The extended mode register 1 stores the data for enabling or disabling the DLL, output driver strength, ODT value selection and
additive latency. The default value of the extended mode register is not defined, therefore the extended mode register must be
written after power‐up for proper operation. Extended mode register 1 is written by asserting LOW on CS#, RAS#, CAS#, WE#, BA1,
and BA2, and HIGH on BA0, and controlling pins A0 – A13. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH
prior to writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete
the write operation to the extended mode register. Mode register contents can be changed using the same command and clock
cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is
used for enabling reduced strength data‐output driver. A3 ‐ A5 determines the additive latency, A2 and A6 are used for ODT value
selection, A7 ‐ A9 are used for OCD control, A10 is used for DQS# disable and A11 is used for RDQS enable.
Integrated Silicon Solution, Inc. – www.issi.com –
6
Rev. 0B, 08/08/2012