IS4346TR16128A Datasheet, PDF (58/81 Pages) Integrated Silicon Solution, Inc – 256Mx8, 128Mx16 2Gb DDR3 SDRAM

IS43/46TR16128A, IS43/46TR16128AL,
IS43/46TR82560A, IS43/46TR82560AL
Parameter
Cumulative error across 12 cycles
Cumulative error across n = 13, 14 . . . 49, 50
cycles
Data Timing
DQS, DQS# to DQ skew, per group, per
access
DQ output hold time from DQS, DQS#
DQ low-impedance time from CK, CK#
DQ high impedance time from CK, CK#
Data setup time to DQS, DQS# referenced to
Vih(ac) / Vil(ac) levels
Data setup time to DQS, DQS# referenced to
Vih(ac) / Vil(ac) levels
Data hold time from DQS, DQS# referenced
to Vih(dc) / Vil(dc) levels
DQ and DM Input pulse width for each input
Data Strobe Timing
DQS,DQS# differential READ Preamble
DQS, DQS# differential READ Postamble
DQS, DQS# differential output high time
DQS, DQS# differential output low time
DQS, DQS# differential WRITE Preamble
DQS, DQS# differential WRITE Postamble
DQS, DQS# rising edge output access time
from rising CK, CK#
DQS and DQS# low-impedance time
(Referenced from RL - 1)
DQS and DQS# high-impedance time
(Referenced from RL + BL/2)
DQS, DQS# differential input low pulse width
DQS, DQS# differential input high pulse width
DQS, DQS# rising edge to CK, CK# rising
edge
DQS, DQS# falling edge setup time to CK,
CK# rising edge
DQS, DQS# falling edge hold time from CK,
CK# rising edge
Command and Address Timing
DLL locking time
Internal READ Command to PRECHARGE
Command delay
Delay from start of internal write transaction to
internal read command
WRITE recovery time
Mode Register Set command cycle time
Mode Register Set command update delay
ACT to internal read or write delay time
PRE command period
ACT to ACT or REF command period
CAS# to CAS# command delay
Symbol
tERR(12per)
tERR(nper)
tDQSQ
tQH
tLZ(DQ)
tHZ(DQ)
tDS(base)
AC175
tDS(base)
AC150
tDH(base)
DC100
tDIPW
tRPRE
tRPST
tQSH
tQSL
tWPRE
tWPST
tDQSCK
tLZ(DQS)
tHZ(DQS)
tDQSL
tDQSH
tDQSS
tDSS
tDSH
tDLLK
tRTP
tWTR
tWR
tMRD
tMOD
tRCD
tRP
tRC
tCCD
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. B1
8/08/2013
DDR3/DDR3L-800 DDR3/DDR3L-1066
Min.
Max.
Min.
Max.
-269
269
-242
242
tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min
tERR(nper)max = (1 + 0.68ln(n)) *
tJIT(per)max
Units
ps
ps
Notes
24
-
200
-
150
0.38
-
0.38
-
-800
400
-600
300
-
400
-
300
See table for Data Setup and Hold
600
-
490
-
0.9
Note
19
0.9
0.3
Note
11
0.3
0.38
-
0.38
-
0.38
-
0.38
-
0.9
-
0.9
-
0.3
-
0.3
-
-400
400
-300
300
-800
400
-600
300
-
400
-
300
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
-0.25
0.25
-0.25
0.25
0.2
-
0.2
-
0.2
-
0.2
-
ps
tCK(avg)
ps
ps
ps
ps
ps
ps
13
13,g
13,14,f
13,14,f
d,17
d,17
d,17
28
Note
Note
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
13,19,g
11,13,g
13,g
13,g
13,f
tCK(avg) 13,14,f
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
13,14,f
29,31
30,31
c
tCK(avg) c,32
tCK(avg) c,32
512
-
512
-
tRTPmin.: max(4nCK, 7.5ns)
tRTPmax.: -
tWTRmin.: max(4nCK, 7.5ns)
tWTRmax.:
15
-
15
-
4
-
4
-
tMODmin.: max(12nCK, 15ns)
tMODmax.:
Standard Speed Bins
Standard Speed Bins
Standard Speed Bins
4
-
4
-
nCK
e
e,18
ns
e,18
nCK
e
e
e
nCK
58