IS61VPS25672A_13 Datasheet, PDF (5/35 Pages) Integrated Silicon Solution, Inc – 256Kx72,512Kx36,1024Kx18 18Mb SYNCHRONOUS PIPELINED,SINGLE CYCLE DESELECT STATIC RAM

IS61VPS25672A, IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
119 BGA PACKAGE PIN CONFIGURATION-512K X 36 (TOP VIEW)
1
2
3
4
5
6
7
A
VDDQ
A
B
NC
A
A
ADSP
A
A
ADSC
A
A
VDDQ
A
NC
C
NC
A
A
VDD
A
A
NC
D
DQc
DQPc
Vss
NC
Vss
DQPb
DQb
E
DQc
DQc
Vss
CE
Vss
DQb
DQb
F
VDDQ
G
DQc
DQc
DQc
Vss
BWc
OE
ADV
Vss
BWb
DQb
DQb
VDDQ
DQb
H
DQc
DQc
Vss
GW
Vss
DQb
DQb
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQd
L
DQd
M
VDDQ
DQd
DQd
DQd
Vss
BWd
Vss
CLK
NC
BWE
Vss
BWa
Vss
DQa
DQa
DQa
DQa
DQa
VDDQ
N
DQd
DQd
Vss
A1*
Vss
DQa
DQa
P
DQd
DQPd
Vss
A0*
Vss
DQPa
DQa
R
NC
A
MODE
VDD
NC
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE
BWx (x=a-d)
BWE
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write Controls
Byte Write Enable
Symbol
OE
ZZ
MODE
TCK, TDO
TMS, TDI
NC
DQa-DQd
DQPa-Pd
VDD
VDDQ
Vss
Pin Name
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
No Connect
Data Inputs/Outputs
Output Power Supply
Power Supply
Output Power Supply
Ground
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. N
02/12/2010