IS42S83200D Datasheet, PDF (49/63 Pages) Integrated Silicon Solution, Inc – 32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM

IS42S83200D, IS42S16160D
IS45S83200D, IS45S16160D
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming
the write burst mode bit (M9) in the mode register to a logic
1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of
the programmed burst length. READ commands access
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9
= 0).
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another bank
while an access command with auto precharge enabled is
executing is not allowed by SDRAMs, unless the SDRAM
supports CONCURRENT AUTO PRECHARGE. ISSI
SDRAMs support CONCURRENT AUTO PRECHARGE.
Four cases where CONCURRENT AUTO PRECHARGE
occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge):
A READ to bank m will interrupt a READ on bank n,
CAS latency later. The PRECHARGE to bank n will
begin when the READ to bank m is registered.
2. Interrupted by a WRITE (with or without auto precharge):
A WRITE to bank m will interrupt a READ on bank n
when registered.DQM should be used three clocks prior
to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to
bank m is registered.
READ With Auto Precharge interrupted by a READ
CLK
COMMAND
T0
NOP
T1
READ - AP
BANK n
T2
NOP
T3
READ - AP
BANK m
T4
NOP
T5
NOP
T6
NOP
T7
NOP
BANK n
Page Active READ with Burst of 4
Internal States
BANK m
Page Active
Interrupt Burst, Precharge
tRP - BANK n
READ with Burst of 4
Idle
tRP - BANK m
Precharge
ADDRESS
DQ
BANK n,
COL a
BANK n,
COL b
DOUT a
DOUT a+1
CAS Latency - 3 (BANK n)
CAS Latency - 3 (BANK m)
DOUT b
DOUT b+1
DON'T CARE
READ With Auto Precharge interrupted by a WRITE
CLK
COMMAND
T0
READ - AP
BANK n
T1
NOP
T2
NOP
T3
T4
T5
NOP
WRITE - AP
BANK m
NOP
T6
NOP
T7
NOP
BANK n
READ with Burst of 4
Internal States ^{Page Active}
BANK m
Page Active
Interrupt Burst, Precharge
tRP - BANK n
WRITE with Burst of 4
Idle
tDPL - BANK m
Write-Back
ADDRESS
DQM
BANK n,
COL a
BANK m,
COL b
DQ
DOUT a
DIN b
DIN b+1
DIN b+2
DIN b+3
CAS Latency - 3 (BANK n)
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com
49
Rev.  B
06/11/09