IS42G32256 Datasheet, PDF (44/52 Pages) Integrated Silicon Solution, Inc – 256K x 32 x 2 (16-Mbit) SYNCHRONOUS GRAPHICS RAM

IS42G32256
ISSI ^®
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLK
CKE HIGH
CS
RAS
CAS
A0-A8
Ra
Rb Ca
Cb
Ra
Ca
A10
A9
Ra
Rb
Ra
WE
DSF
DQM
DQ: CLOCK
LATENCY = 2
DQ: CLOCK
LATENCY = 3
Qa0 Qa1 Qb0 Qb1 Db2 Db3
Qa0 Qa1 Qb0 Qb1 Db2 Db3
Da0 Da1
Da0 Da1
ROW ACTIVE
(A-BANK)
ROW ACTIVE
READ
(B-BANK)
WITHOUT
AUTO
READ _PRECHARGE
WITH AUTO _(B-BANK)
PRECHARGE
(A-BANK)
AUTO
PRECHARGE
START POINT
(A-BANK)
PRECHARGE
(B-BANK)
ROW ACTIVE
(A-BANK)
WRITE WITH
AUTO PRECHARGE
(A-BANK)
: DON’T CARE
Note:
1. When Read (Write) command with auto precharge is issued at A-Bank after A and B Bank activation.
— If Read (Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank
auto precharge will start at the next cycle of B Bank read command input point.
— Any command can not be issued at A Bank during tRP after A Bank auto precharge starts.
Figure 28. Read and Write Cycle with Auto Precharge II at Burst Length = 4
44
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C
09/10/98