IS61SP25616 Datasheet, PDF (4/15 Pages) Integrated Silicon Solution, Inc – 256K x 16, 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM

IS61SP25616
IS61SP25618
PIN CONFIGURATION
ISSI ^®
119-pin PBGA (Top View)
1
2
3
4
5
6
7
A
VCCQ A6
A4
ADSP
A8
A16 VCCQ
B
NC
CE2
A3
ADSC
A9
CE2
NC
C
NC
A7
A2
VCC
A12
A15
NC
D
DQ9
NC
GND
NC
GND DQP1
NC
E
NC
DQ10 GND
CE
GND
NC
DQ8
F
VCCQ NC
GND
OE
GND DQ7 VCCQ
G
NC
DQ11 BW2 ADV GND
NC
DQ6
H
DQ12
NC
GND
GW
GND DQ5
NC
J
VCCQ VCC
NC
VCC
NC
VCC VCCQ
K
NC
DQ13 GND CLK GND
NC
DQ4
L
DQ14
NC
GND
NC
BW1 DQ3
NC
M
VCCQ DQ15
GND
BWE
GND
NC VCCQ
N
DQ16
NC
GND
A1
GND DQ2
NC
P
NC DQP2 GND
A0
GND
NC
DQ1
R
NC
A5 MODE VCC GND A13
NC
T
NC
A11
A10
NC
A14
A17
ZZ
U
VCCQ NC
NC
NC
NC
NC VCCQ
100-Pin TQFP
NC
NC
NC
VCCQ
GND
NC
NC
DQ9
DQ10
GND
VCCQ
DQ11
DQ12
NC
VCC
NC
GND
DQ13
DQ14
VCCQ
GND
DQ15
DQ16
DQP2
NC
GND
VCCQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A17
NC
NC
VCCQ
GND
NC
DQP1
DQ8
DQ7
GND
VCCQ
DQ6
DQ5
GND
NC
VCC
ZZ
DQ4
DQ3
VCCQ
GND
DQ2
DQ1
NC
NC
GND
VCCQ
NC
NC
NC
256K x 18
PIN DESCRIPTIONS
A0, A1
A2-A17
CLK
ADSP
ADSC
ADV
BW1-BW2
BWE
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
GW
Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
DQ1-DQ16 Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
VCC
+3.3V Power Supply
GND
Ground
VCCQ
Isolated Output Buffer Supply: +3.3V
ZZ
Snooze Enable
DQP1-DQP2 Parity Data I/O DQP1 is parity for DQ1-8;
DQP2 is parity for DQ9-16
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01