IS61DDB44M18A Datasheet, PDF (4/31 Pages) Integrated Silicon Solution, Inc – Synchronous pipeline read with late write operation

IS61DDB44M18A
IS61DDB42M36A
SRAM Features description
Block Diagram
Data
Register-
Burst4
Addresses : ^{19 (20)}
SA
2
SA₀,SA₁
Add Reg &
Burst
Control
21 (22)
LD#
R/W#
BW_x#
4 (2)
Control
Logic
36(18)
36x4 (18x4)
Write
Driver
36x4 (18x4)
2M x 36
(4M x 18)
Memory Array
36x4
144
36
(18x4)
(72)
(18)
Output
Reg
K
K#
Clock
C
Generator
C#
/D_off
Select Output Control
36 (18)
DQ(Data-out
&Data-In)
CQ, CQ#
(Echo Clocks)
Note: Numerical values in parentheses refer to the x18 device configuration.
Read Operations
The SRAM operates continuously in a burst-of-four mode. Read cycles are started by registering R/W# in active high
state at the rising edge of the K clock. R/W# can be activated every other cycle because two full cycles are required to
complete the burst-of-four read in DDR mode. A second set of clocks, C and C#, are used to control the timing to the
outputs. A set of free-running echo clocks, CQ and CQ#, are produced internally with timings identical to the data-outs.
The echo clocks can be used as data capture clocks by the receiver device.
When the C and C# clocks are connected high, the K and K# clocks assume the function of those clocks. In this case,
the data corresponding to the first address is clocked one and half cycles later by the rising edge of the K# clock. The
data corresponding to the second burst is clocked two cycles later by the following rising edge of the K clock. The third
data-out is clocked by the subsequent rising edge of the K# clock, and the fourth data-out is clocked by the
subsequent rising edge of the K clock.
Whenever LD# is low, a new address is registered at the rising edge of the K clock. A NOP operation (LD# is high)
does not terminate the previous read. The output drivers disable automatically to a high state.
Integrated Silicon Solution, Inc.- www.issi.com
4
Rev. A
12/08/2014