IS25C32B Datasheet, PDF (4/15 Pages) Integrated Silicon Solution, Inc – 32K-BIT SPI AUTOMOTIVE EEPROM

IS25C32B-Automotive
STATUS REGISTER
The status register contains 8-bits for write protection
control and write status. (See Table 1). It is the only
region of memory other than the main array that is ac-
cessible by the user.
Table 1. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0
WPEN X X X BP1 BP0 WEN RDY
Notes:
1. X = Don't care bit.
2. During internal write cycles, bits 0 to 7 are temporarily 1's.
The Status Register is Read-Only if either: a) Hardware
Write Protection is enabled or b) WEN is set to 0. If
neither is true, it can be modified by a valid instruction.
Ready (RDY), Bit 0: When RDY = 1, it indicates that
the device is busy with a write cycle. RDY = 0 indicates
that the device is ready for an instruction. If RDY = 1,
the only command that will be handled by the device is
Read Status Register.
Write Enable (WEN), Bit 1: This bit represents the
status of device write protection. If WEN = 0, the Status
Register and the entire array is protected from modifi-
cation, regardless of the setting of WPEN, WP pin, or
block protection. The only way to set WEN to 1 is via
the Write Enable command (WREN). WEN is reset to 0
upon power-up.
Block Protect (BP1, BP0), Bits 2-3: Together, these
bits represent one of four block protection configura-
tions implemented for the memory array. (See Table 2
for details.)
BP0 and BP1 are non-volatile cells similar to regular
array cells, and factory programmed to 0. The block
of memory defined by these bits is always protected,
regardless of the setting of WPEN, WP , or WEN.
Table 2. Block Protection
Status
Register
Bits
Array Addresses Protected
Level BP1 BP0
IS25C32B
0
00
None
1(1/4)
01

0C00h
-0FFFh
2(1/2)
10

0800h
-0FFFh
3(All)
11

0000h
-0FFFh
Don’t Care, Bits 4-6: Each of these bits can receive ei-
ther 0 or 1, but values will not be retained. When these
bits are read from the register, they are always 0.
Write Protect Enable (WPEN), Bit 7: This bit can be
used in conjunction with WP pin to enable Hardware
Write Protection, which causes the Status Register to
be read-only. The memory array is not protected by this
mode. Hardware Write Protection requires that WP = 0
and WPEN = 1; it is disabled otherwise. Note: WPEN
cannot be changed from 1 to 0 if the WP pin is already
set to Low. (See Table 4 for data protection relation-
ship)
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Integrated Silicon Solution, Inc. — www.issi.com
Advanced Information  Rev.  00B
08/27/09