IS42S16400J-6TL Datasheet, PDF (37/60 Pages) Integrated Silicon Solution, Inc – 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

IS42S16400J
IS45S16400J
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto precharge):
A READ to bank m will interrupt a WRITE on bank n
when registered, with the data-out appearing CAS latency
later. The PRECHARGE to bank n will begin after twr
is met, where twr begins when the READ to bank m is
registered. The last valid WRITE to bank n will be data-in
registered one clock prior to the READ to bank m.
4. Interrupted by a WRITE (with or without auto precharge):
AWRITE to bank m will interrupt a WRITE on bank n when
registered. The PRECHARGE to bank n will begin after
twr is met, where twr begins when the WRITE to bank
m is registered. The last valid data WRITE to bank n
will be data registered one clock prior to a WRITE to
bank m.
Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
NOP
WRITE - AP
BANK n
NOP
READ - AP
BANK m
NOP
NOP
NOP
NOP
BANK n
Page Active WRITE with Burst of 4
Internal States
BANK m
Page Active
Interrupt Burst, Write-Back
tWR - BANK n
READ with Burst of 4
Precharge
tRP - BANK n
tRP - BANK m
Precharge
ADDRESS
BANK n,
COL a
BANK m,
COL b
DQ
DIN a
DIN a+1
DOUT b
DOUT b+1
CAS Latency - 3 (BANK m)
DON'T CARE
Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
NOP
WRITE - AP
BANK n
NOP
NOP
WRITE - AP
BANK m
NOP
NOP
NOP
BANK n
Page Active
Internal States
BANK m
WRITE with Burst of 4
Page Active
Interrupt Burst, Write-Back
tWR - BANK n
WRITE with Burst of 4
Precharge
tRP - BANK n
tRP - BANK m
Write-Back
ADDRESS
BANK n,
COL a
BANK m,
COL b
DQ
DIN a
DIN a+1
DIN a+2
DIN b
DIN b+1
DIN b+2
DIN b+3
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com
37
Rev. D
5/28/2013