IS43LR16160G Datasheet, PDF (33/45 Pages) Integrated Silicon Solution, Inc – Fully differential clock inputs

IS43/46LR16160G
Write
The WRITE command is used to initiate a Burst Write access to an active row. The value of BA0, BA1 selects the bank and address inputs
select the starting column location.
The value of A10 determines whether or not auto precharge is used.If autoprecharge is selected, the row being accessed will be
precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent access. Input data
appearing on the data bus, is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given
DM signal is registered low, the corresponding data will be written to the memory; if the DM signal is registered high, the corresponding
data-inputs will be ignored, and a write will not be executed to that byte/column location. The memory controller drives the DQS during
write operations. The initial low state of the DQS is known as the write preamble and the low state following the last data-in element is write
postamble. Upon completion of a burst, assuming no new commands have been initiated, the I/O's will stay high-Z and any additional input
data will be ignored.
Figure21 : Write command
CLK
/CLK
CKE
/CS
/RAS
/CAS
/WE
A0~A8
CA
A10
BA0, BA1
BA
Notes :
1. CA : Column address
2. BA : Bank address
3. A10=High : Enable Auto precharge
A10=Low : Disable Auto precharge
Don’ t care
Figure22 : Write Burst (BL=4)
T0
/CLK
CLK
Command
WRITE
T1 T1n T2 T2n T3
NOP
WRITE
A ddress
DQS
DQ
Bank a
COL n
tDQSS
tDQSH
Bank a
COL m
tWPST
tWPRES
tWPRE
tDS
tDH
D IN
D IN
DIN
D IN
n
n+1
n+2
n+3
DM
Don_’ t care
Notes:
1. Din n = Data-In from Column n.
Rev. A | November 2013
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