IS43LR32320B Datasheet, PDF (32/47 Pages) Integrated Silicon Solution, Inc – 8M x 32Bits x 4Banks Mobile DDR SDRAM

IS43/46LR32320B
Figure18 : Random Read access
T0
T1
T2
T3
T4
T5
/ CLK
CLK
Command
READ
READ
READ
READ
NOP
NOP
NOP
A ddress
Bank a
COL n
DQS
Bank a
COL m
CL=3
Bank a
COL p
Bank a
COL q
DQ
Don’t care
DOUT
n
D OUT
n+1
DOUT
m
D OUT
m +1
D OUT
p
DOUT
p+1
D OUT
q
D OUT
q+1
Notes:
1. Dout n or m,p,q = Data-Out from Column n or m,p,q
2. BL=2,4,8,16 (if 4,8 or 16, the following burst interrupts the previous)
3. Reads are to an Active row in any bank.
4. Shown with nominal tAC, tDQSCK and tDQSQ
Truncated Reads
Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure16. The BURST TERMINATE
latency is equal to the READ (CAS) latency, i.e., the BURST TERMINATE command should be issued x cycles after the READ command,
where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is
necessary, the BURST TERMINATE command must be used.
A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank provided that auto precharge was not
activated. The PRECHARGE command should be issued x cycles after the READ command, where x equals the number of desired data
element pairs (pairs are required by the n-prefetch architecture). This is shown in Figure (READ to PRECHARGE). Following the
PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.
Figure19 : Read Burst terminate (BL=4,8 or 16)
T0
T1
T2
T3
T4
/CLK
CLK
Command
READ
BST
NOP
NOP
NOP
A ddress
Bank a
COL n
CL= 3
DQS
DQ
Don’ t care
DOUT
n
D OUT
n+1
Notes:
1. Dout n = Data-Out from Column n
2. CKE=high
3. Shown with nominal tAC, tDQSCK and tDQSQ
Rev. B | Jan 2014
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