IS42VM32400H Datasheet, PDF (30/33 Pages) Integrated Silicon Solution, Inc – 1M x 32Bits x 4Banks Mobile Synchronous DRAM

IS42/45SM/RM/VM32400H
Advanced Information
Special Operation for Low Power Consumption
Temperature Compensated Self Refresh
Temperature Compensated Self Refresh allows the controller to program the Refresh interval during SELF REFRESH mode, according to
the case temperature of the Mobile SDRAM device. This allows great power savings during SELF REFRESH during most operating
temperature ranges. Only during extreme temperatures would the controller have to select a TCSR level that will guarantee data during
SELF REFRESH.
Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on
temperature. At higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed
more often. Historically, during Self Refresh, the refresh rate has been set to accommodate the worst case, or highest temperature
range expected.
Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to
accommodate the higher temperatures.
This temperature compensated refresh rate will save power when the DRAM is operating at normal temperatures.
Partial Array Self Refresh
For further power savings during SELF REFRESH, the PASR feature allows the controller to select the amount of memory that will be
refreshed during SELF REFRESH. The refresh options are All Banks, Two Banks (bank a and b), One Bank (bank a), Half of One Bank
(1/2 of bank a), or Quarter of One Bank (1/4 of bank a). WRITE and READ commands can still occur during standard operation, but
only the selected banks will be refreshed during SELF REFRESH. Data in banks that are disabled will be lost.
Deep Power Down
Deep Power Down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of
the devices. Data will not be retained once the device enters Deep Power Down Mode.
This mode is entered by having all banks idle then /CS and /WE held low with /RAS and /CAS held high at the rising edge of the clock,
while CKE is low. This mode is exited by asserting CKE high.
Rev. 00A | Nov. 2014
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