IS25LP080D Datasheet, PDF (28/108 Pages) Integrated Silicon Solution, Inc – SERIAL FLASH MEMORY WITH 133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE

8.2 FAST READ OPERATION (FRD, 0Bh)
IS25LP080D
IS25WP080D/040D/020D
The FAST READ (FRD) instruction is used to read memory data at up to a 133MHz clock.
The FAST READ instruction code is followed by three address bytes (A23 - A0) and dummy cycles (configurable,
default is 8 clocks), transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first
data byte from the address is shifted out on the SO line, with each bit shifted out at a maximum frequency fCT,
during the falling edge of SCK.
The first byte addressed can be at any memory location. The address is automatically incremented by one after
each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the
000000h address, allowing the entire memory to be read with a single FAST READ instruction. The FAST READ
instruction is terminated by driving CE# high (VIH).
If the FAST READ instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction
is ignored without affecting the current cycle.
Figure 8.2 Fast Read Sequence
CE #
SCK
SI
Mode 3 ^{0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31}
Mode 0
Instruction = 0Bh
3-byte Address
23 22 21 ^... 3 2 1 0
SO
High Impedance
CE #
SCK
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 ...
SI
Dummy Cycles
t_V
Data Out
SO
7 6 5 4 3 2 1 0 ^...
Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.
Integrated Silicon Solution, Inc.- www.issi.com
28
Rev. A
09/02/2016