IS43R16800CC Datasheet, PDF (27/37 Pages) Integrated Silicon Solution, Inc – Commands entered on each positive CLK edge

Preliminary
I_IS43R16800CC
Zentel Electronics Corporation
A3S56D30/40ETP
256M Double Data Rate Synchronous DRAM
BURST INTERRUPTION
[Read Interrupted by Read]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed.
READ to READ interval is minimum 1CLK.
Read Interrupted by Read (BL=8, CL=2)
/CLK
CLK
Command
READ READ
READ
READ
A0-9,11
Yi Yj
Yk
Yl
A10
00
0
0
BA0,1
00 00
10
01
DQS
DQ
Qai0 Qai1 Qaj0 Qaj1 Qaj2 Qaj3 Qak0 Qak1 Qak2 Qak3 Qak4 Qak5 Qal0 Qal1 Qal2 Qal3 Qal4 Qal5 Qal6 Qal7
[Read Interrupted by precharge]
Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is
minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency.
As a result, READ to PRE interval determines valid data length to be output. The figure below
shows examples of BL=8. _{Read Interrupted by Precharge (BL=8)}
/CLK
CLK
Command
READ
PRE
DQS
DQ
Q0 Q1 Q2 Q3 Q4 Q5
CL=2.0
Command
DQS
DQ
READ
PRE
Q0 Q1 Q2 Q3
Command
DQS
DQ
READ PRE
Q0 Q1
I^Dnt^Deg^Rra^Ste^Dd^RS^Aili^Mcon^(RS^eo^vlu^.1tio^.1n⁾, Inc.
27
Rev. 
06/01/09