IS43TR16640B Datasheet, PDF (25/88 Pages) Integrated Silicon Solution, Inc – Programmable CAS Latency

IS43/46TR16640B, IS43/46TR16640BL
IS43/46TR81280B, IS43/46TR81280BL
2.4.7.2 Procedure Description
The Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. When entering write leveling
mode, the DQ pins are in undefined driving mode. During write leveling mode, only NOP or DESELECT commands are
allowed, as well as an MRS command to exit write leveling mode. Since the controller levels one rank at a time, the output
of other ranks must be disabled by setting MR1 bit A12 to 1.
The Controller may assert ODT after tMOD, at which time the DRAM is ready to accept the ODT signal.
The Controller may drive DQS low and DQS# high after a delay of tWLDQSEN, at which time the DRAM has applied on-
die termination on these signals. After tDQSL and tWLMRD, the controller provides a single DQS, DQS# edge which is
used by the DRAM to sample CK - CK# driven from controller. tWLMRD(max) timing is controller dependent.
DRAM samples CK - CK# status with rising edge of DQS - DQS# and provides feedback on the DQ bus asynchronously
after tWLO timing. In this product, the DQ0 for x8 or DQ0 and DQ8 for x16 ("prime DQ bit(s)") provide the leveling
feedback. The DRAM's remaining DQ bits are driven Low statically after the first sampling procedure. There is a DQ
output uncertainty of tWLOE defined to allow mismatch on DQ bits. The tWLOE period is defined from the transition of the
earliest DQ bit to the corresponding transition of the latest DQ bit. There are no read strobes (DQS/DQS#) needed for
these DQs. Controller samples incoming DQ and decides to increment or decrement DQS - DQS# delay setting and
launches the next DQS/DQS# pulse after some time, which is controller dependent. Once a 0 to 1 transition is detected,
the controller locks DQS - DQS# delay setting and write leveling is achieved for the device. Figure 2.4.7.2 describes the
timing diagram and parameters for the overall Write Leveling procedure.
CK#⁽⁵⁾
CK
CMD
(2)
MRS
ODT
diff_DQS⁽⁴⁾
(3)
NOP
tMOD
NOP
tWLDQSEN
NOP
tWLS
T1
tWLH
NOP
NOP
NOP
tDQSL⁽⁶⁾
tDQSH⁽⁶⁾
tWLS
T2
tWLH
NOP
NOP
NOP
NOP
tDQSL⁽⁶⁾
tDQSH⁽⁶⁾
NOP
Prime DQ⁽¹⁾
Late Remaining
DQs
Early Remaining
DQs
tWLMRD
tWLO
tWLO
tWLO
tWLOE
tWLO
Figure 2.4.7.2 Write leveling sequence [DQS - DQS# is capturing CK-CK# low at T1 and CK-CK# high at T2]
Undefined
Driving Mode
Time Break DON’T CARE
Notes:
1. The JEDEC specification for DDR3 DRAM has the option to drive leveling feedback on a single prime DQ or all DQs. For best compatibility with
future DDR3 products, applications should use the lowest order DQ for each byte lane (DQ0 for x8, or DQ0 and DQ8 for x16).
2. MRS: Load MR1 to enter write leveling mode.
3. NOP: NOP or Deselect.
4. diff_DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. DQS is shown with solid line, DQS# is shown
with dotted line.
5. CK, CK# : CK is shown with solid dark line, where as CK# is drawn with dotted line.
6. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the max pulse width is
system dependent.
Integrated Silicon Solution, Inc. – www.issi.com –
25
Rev. C1
11/12/2014