IS66WVE51216EALL Datasheet, PDF (23/31 Pages) Integrated Silicon Solution, Inc – Asynchronous and page mode interface

IS66WVE51216EALL/BLL/CLL
IS67WVE51216EALL/BLL/CLL
Table14 . Load Configuration Register Timing Requirements
Symbol
Parameter
-55
Min
Max
-70
Min
Max
Unit Note
t_AS
Address setup time
0
0
ns
t_AW
Address valid to end of write
55
70
ns
t_CDZZ Chip deselect to ZZ# LOW
5
5
ns
t_CEM
Maximum CE# pulse width
15
15
us
t_CW
Chip enable to end of write
55
70
ns
t_WC
Write cycle time
55
70
ns
t_WP
Write pulse width
46
46
ns
t_WR
Write recovery time
0
0
ns
1
t_ZZWE ZZ# LOW to WE# LOW
10
500
10
500
ns
Note:
1. Write address is valid prior to or coincident with CE# LOW transition and is valid prior to or coincident with
CE# HIGH transition.
Table15 . DPD Timing Requirements
Symbol
Parameter
-55
-70
Unit
Min
Max
Min
Max
t_CDZZ
Chip deselect to ZZ# LOW
5
5
ns
t_R
Deep Power-down recovery 150
150
us
t_ZZ(MIN) Minimum ZZ# pulse width
10
10
us
Notes
Table16 . Initialization Timing Requirements
Symbol
Parameter
-55
-70
Unit
Min
Max
Min
Max
t_PU
Initialization Period (required
before normal operations)
150
150
us
Notes
Rev. 0D | November 2014
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