IS49NLS96400 Datasheet, PDF (23/34 Pages) Integrated Silicon Solution, Inc – 576Mb (x9, x18) Separate I/O RLDRAM 2 Memory

IS49NLS96400,IS49NLS18320
0
1
2
3
4
t_CKH
t_CKL
t_CK
CK#
CK
QKx#
QKx
t_RC
Command
AREFx
AREFy
NOP
NOP
NOP
t_RC
Bank Address
BAx
BAy
5
ANYCOMx
BAx
AREF example in t_RC(t_CK)=5 option: Configuration=5
Don’t Care
6
ANYCOMy
BAy
Command Truth Table
Operation
Code
CS#
WE#
Device DESELECT/No Operation
DESL/NOP H
X
Mode Register Set
MRS
L
L
Read
READ
L
H
Write
WRITE
L
L
Auto Refresh
AREF
L
H
Notes:
1. X = "Don't Care;" H = logic HIGH; L = logic LOW; A = Valid Address; BA = Valid Bank Address.
2. During MRS, only address inputs A0‐A17 are used.
3. Address width changes with burst length.
4. All input states or sequences not shown are illegal or reserved.
5. All command and address inputs must meet setup and hold times around the rising edge of CK.
REF#
X
L
H
H
L
Ax
BAx
X
X
OPCODE X
A
BA
A
BA
X
BA
Integrated Silicon Solution, Inc. – www.issi.com –
23
Rev. 00E, 06/20/2012