IS42S16800A1 Datasheet, PDF (23/63 Pages) Integrated Silicon Solution, Inc – 8Meg x16 128-MBIT SYNCHRONOUS DRAM

IS42S16800A1
ISSI ^®
Burst write operations will be terminated by the Precharge command. The last write data that will be properly stored in the
device is that write data that is presented to the device a number of clock cycles prior to the Precharge command equal to the
Data-in to Precharge delay, t_DPL.
Precharge Termination of a Burst Write
(Burst Length = 8, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
COMMAND ^NOP
NOP
WRITE Ax₀
NOP
NOP
NOP
Precharge A
NOP
NOP
DQM
CAS latency = 2
t_CK2, DQs
CAS latency = 3
t_CK3, DQs
DIN Ax₀
DIN Ax₀
DIN Ax₁
DIN Ax₁
t_DPL‡
DIN Ax₂
t_DPL‡
DIN Ax₂
‡ t_DPL is an asynchronous timing and may be completed in one or two clock cycles
depending on clock cycle time.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
©
23
Rev. 00B
N
05/01/06