IS89C51 Datasheet, PDF (20/48 Pages) Integrated Silicon Solution, Inc – CMOS SINGLE CHIP 8-BIT MICROCONTROLLER with 4-Kbytes of FLASH

IS89C51
Table 7. Commonly Used Baud Rates Generated by Timer 1
Baud Rate
Mode 0 Max: 1 MHz
Mode 2 Max: 375K
Modes 1, 3: 62.5K
19.2K
9.6K
4.8K
2.4K
1.2K
137.5
110
110
fOSC
12 MHz
12 MHz
12 MHz
11.059 MHz
11.059 MHz
11.059 MHz
11.059 MHz
11.059 MHz
11.986 MHz
6 MHz
12 MHz
SMOD
X
1
1
1
0
0
0
0
0
0
0
ISSI ^®
Timer 1
C/T
Mode
Reload Value
X
X
X
X
X
X
0
2
FFH
0
2
FDH
0
2
FDH
0
2
FAH
0
2
F4H
0
2
E8H
0
2
1DH
0
2
72H
0
1
FEEBH
More About Mode 0
Serial data enters and exits through RXD. TXD outputs the
shift clock. Eight data bits are transmitted/received, with
the LSB first. The baud rate is fixed at 1/12 the oscillator
frequency.
Figure 12 shows a simplified functional diagram of the
serial port in Mode 0 and associated timing.
Transmission is initiated by any instruction that uses SBUF
as a destination register. The "write to SBUF" signal at
S6P2 also loads a 1 into the ninth position of the transmit
shift register and tells the TX Control block to begin a
transmission. The internal timing is such that one full
machine cycle will elapse between "write to SBUF" and
activation of SEND.
SEND transfer the output of the shift register to the
alternate output function line of P3.0, and also transfers
SHIFT CLOCK to the alternate output function line of P3.1.
SHIFT CLOCK is low during S3, S4, and S5 of every
machine cycle, and high during S6, S1, and S2. At S6P2
of every machine cycle in which SEND is active, the
contents of the transmit shift register are shifted one
position to the right.
As data bits shift out to the right, 0s come in from the left.
When the MSB of the data byte is at the output position of
the shift register, the 1 that was initially loaded into the
ninth position is just to the left of the MSB, and all positions
to the left of that contain 0s. This condition flags the TX
Control block to do one last shift, then deactivate SEND
and set TI. Both of these actions occur at S1P1 of the tenth
machine cycle after "write to SBUF."
Reception is initiated by the condition REN = 1 and
RI = 0. At S6P2 of the next machine cycle, the RX Control
unit writes the bits 11111110 to the receive shift register
and activates RECEIVE in the next clock phase.
RECEIVE enables SHIFT CLOCK to the alternate output
function line of P3.1. SHIFT CLOCK makes transitions at
S3P1 and S6P1 of every machine cycle. At S6P2 of every
machine cycle in which RECEIVE is active, the contents of
the receive shift register are shifted on position to the left.
The value that comes in from the right is the value that was
sampled at the P3.0 pin at S5P2 of the same machine
cycle.
As data bits come in from the right, 1s shift out to the left.
When the 0 that was initially loaded into the right-most
position arrives at the left-most position in the shift register,
it flags the RX Control block to do one last shift and load
SBUF. At S1P1 of the tenth machine cycle after the write
to SCON that cleared RI, RECEIVE is cleared and RI is set.
More About Mode 1
Ten bits are transmitted (through TXD), or received (through
RXD): a start bit (0), eight data bits (LSB first), and a stop
bit (1). On receive, the stop bit goes into RB8 in SCON. In
the IS89C51 the baud rate is determined by the Timer 1
overflow rate.
Figure 13 shows a simplified functional diagram of the
serial port in Mode 1 and associated timings for transmit
and receive.
Transmission is initiated by any instruction that uses SBUF
as a destination register.
20
1-800-379-4774 — Integrated Silicon Solution, Inc.
MC016-1C
11/21/98